CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 5

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

CYNSE70256
LIST OF FIGURES
(continued)
Figure 10-39. Timing Diagram for Globally Winning Device in Block Number 3 ................................... 58
Figure 10-40. Timing Diagram for Devices Below the Winning Device in Block Number 3
Except Device 14 (the Last Device)....................................................................................................... 59
Figure 10-41. Timing Diagram for Device Number 2
in Block Number 3 (Device 14 in a Depth-Cascaded Table) ................................................................. 60
Figure 10-42. ×144 Table with Fifteen Devices ..................................................................................... 61
Figure 10-43. Hardware Diagram for a Table with Four Devices .......................................................... 62
Figure 10-44. Timing Diagram for 288-bit Search Device Number 0..................................................... 63
Figure 10-45. Timing Diagram for 288-bit Search Device Number 1..................................................... 64
Figure 10-46. Timing Diagram for 288-bit Search Device Number 3 (Last Device) .............................. 65
Figure 10-47. ×288 Table with Four Devices......................................................................................... 66
Figure 10-48. Hardware Diagram for a Table with Fifteen Devices ....................................................... 67
Figure 10-49. Hardware Diagram for a Block of up to Four Devices ..................................................... 68
Figure 10-50. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) ................. 69
Figure 10-51. Timing Diagram for Each Device Above the Winning Device in Block Number 1 ........... 70
Figure 10-52. Timing Diagram for Globally Winning Device in Block Number 1 ................................... 71
Figure 10-53. Timing Diagram for Devices Below the Winning Device in Block Number 1 ................... 72
Figure 10-54. Timing Diagram for Devices Above the Winning Device in Block Number 2 .................. 73
Figure 10-55. Timing Diagram for Globally Winning Device in Block Number 2 ................................... 74
Figure 10-56. Timing Diagram for Devices Below the Winning Device in Block Number 2 ................... 75
Figure 10-57. Timing Diagram for Devices Above the Winning Device in Block Number 3 .................. 76
Figure 10-58. Timing Diagram for Globally Winning Device in Block Number 3 ................................... 77
Figure 10-59. Timing Diagram for Devices Below the Winning Device in Block Number 3
Except Device 14 (Last Device)............................................................................................................. 78
Figure 10-60. Timing Diagram of the Last Device in Block Number 3 (Device 14 in the Table)............ 79
Figure 10-61. ×288 Table with Fifteen Devices ..................................................................................... 80
Figure 10-62. Timing Diagram for Mixed Search (One Device)............................................................. 81
Figure 10-63. Multiwidth Configurations Example ................................................................................. 81
Figure 10-64. Timing Diagram of Learn (Except on the Last Device [TLSZ = 01])................................ 83
Figure 10-65. Timing Diagram of Learn on Device Number 3 (TLSZ = 01)........................................... 83
Figure 11-1. Hardware Diagram for a Block of up to Four Devices ....................................................... 84
Figure 11-2. Depth Cascading four Blocks ............................................................................................ 85
Figure 11-3. FULL Signal Generation in a Cascaded Table.................................................................. 86
Figure 12-1. Hardware Diagram of a Block of Four Devices ................................................................. 87
Figure 12-2. SRAM Read Through Device Number 0 in a Block of Four Devices ................................ 88
Figure 12-3. SRAM Read Timing for Device Number 7 in a Block of Four Devices .............................. 88
Figure 12-4. Hardware Diagram of Fifteen Devices Using Four Blocks ................................................ 89
Figure 12-5. SRAM Read Through Device Number 0 in a Bank of Fifteen Devices
(Device Number 0 Timing)..................................................................................................................... 90
Figure 12-6. SRAM Read Through Device Number 0 in a Bank of Fifteen Devices
(Device Number 14 Timing)................................................................................................................... 90
Figure 12-7. Hardware Diagram of a Block of Four Devices ................................................................. 91
Figure 12-8. SRAM Write Through Device Number 0 in a Block of Four Devices................................. 91
Figure 12-9. SRAM Write Timing for Device Number 3 in Block of Four Devices ................................. 92
Figure 12-10. Table of Fifteen Devices (Four Blocks) ........................................................................... 93
Figure 12-11. SRAM Write Through Device Number 0
in Bank of Fifteen Devices (Device 0 Timing)........................................................................................ 93
Figure 12-12. SRAM Write Through Device Number 0
in Bank of Fifteen CYNSE70256 Devices (Device Number 14 Timing)................................................. 94
Document #: 38-02035 Rev. *E
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