CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 47

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The logical 144-bit Search operation is shown in Figure 10-28. The entire table (four devices of 144-bit entries) is compared to a
144-bit word K (presented on the DQ bus in cycles A and B of the command) using the GMR and local mask bits. The GMR is
the 144-bit word specified by the even and odd global mask pair selected by the GMR index in the command’s cycle A. The 144-
bit word K (presented on the DQ bus in cycles A and B of the command) is also stored in the even and odd comparand registers
specified by the comparand register index in command cycle B. In ×144 configurations, the even and odd comparand registers
can be subsequently used by the Learn command in only one of the devices (the first non-full device). The word K (presented on
the DQ bus in cycles A and B of the command) is compared to each entry in the table starting at location 0. The first matching
entry’s location, address L, is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see “SRAM
Addressing” on page 86). The global winning device will drive the bus in a specific cycle. On global miss cycles the device with
LRAM = 1 (the default driving device for the SRAM bus) and LDEV = 1 (the default driving device for SSF and SSV signals) will
be the default driver for such missed cycles.
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 144-bit
searches in ×144-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 144-bit Search
command cycle (two CLK2X cycles) is shown in Table 10-17.
Table 10-17. Search Latency from Instruction to SRAM Access Cycle
For one to four devices in the table and TLSZ = 01, Search latency from command to SRAM access cycle is 5. In addition, SSV
and SSF shift further to the right for different values of HLAT, as specified in Table 10-18.
Table 10-18. Shift of SSF and SSV from SADR
Note:
Document #: 38-02035 Rev. *E
16. During 144-bit searches of 144-bit-configured tables, the Search hit will always be at an even address.
Number of Devices
1–15 (TLSZ = 10)
1–4 (TLSZ = 01)
Must be same in each of the banks
for each of the four devices
HLAT
Will be same in each of the banks
000
001
010
100
101
011
110
111
Comparand Register (odd)
Comparand Register (even)
71
of the four devices
A
B
Figure 10-28. ×144 Table with Four Devices
Max Table Size
256K × 144 bits
960K × 144 bits
[16]
0
524,286
Location
address
GMR
L
0
2
4
6
K
CFG = 0101010101010101
143
143
(144-bit configuration)
Even
A
Number of CLK Cycles
Odd
B
0
Latency in CLK Cycles
0
1
2
3
4
5
6
7
0
(First matching entry)
5
6
CYNSE70256
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