CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 2

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CYNSE70256-66BHC

Manufacturer Part Number
CYNSE70256-66BHC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYNSE70256-66BHC

Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Package Type
BGA
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CYNSE70256-66BHC
Manufacturer:
TI
Quantity:
8
Part Number:
CYNSE70256-66BHC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
CYNSE70256
CONTENTS
1.0 OVERVIEW ...................................................................................................................................... 8
2.0 FEATURES ...................................................................................................................................... 8
3.0 FUNCTIONAL DESCRIPTION ......................................................................................................... 9
3.1 Command Bus and DQ Bus ............................................................................................................. 9
3.2 Database Entry (Data and Mask Arrays) .......................................................................................... 9
3.3 Arbitration Logic .............................................................................................................................. 10
3.4 Pipeline and SRAM Control ............................................................................................................ 10
3.5 Full Logic ........................................................................................................................................ 10
4.0 SIGNAL DESCRIPTIONS .............................................................................................................. 10
5.0 CLOCKS ......................................................................................................................................... 12
6.0 PHASE-LOCK LOOP USAGE ....................................................................................................... 13
7.0 REGISTERS ................................................................................................................................... 13
7.1 Comparand Registers ..................................................................................................................... 13
7.2 Mask Registers ............................................................................................................................... 14
7.3 Search Successful Registers (SSR[0:7]) ........................................................................................ 14
7.4 Command Register ......................................................................................................................... 15
7.5 Information Register ....................................................................................................................... 16
7.6 Read Burst Address Register ......................................................................................................... 16
7.7 Write Burst Address Register Description ...................................................................................... 17
7.8 NFA Register .................................................................................................................................. 17
8.0 NSE ARCHITECTURE AND OPERATION OVERVIEW ............................................................... 17
9.0 DATA AND MASK ADDRESSING ................................................................................................ 19
10.0 COMMANDS ................................................................................................................................ 19
10.1 Command Codes .......................................................................................................................... 19
10.2 Commands and Command Parameters ....................................................................................... 19
10.3 Read Command ............................................................................................................................ 20
10.4 Write Command ............................................................................................................................ 22
10.5 Parallel Write ................................................................................................................................ 24
10.6 Search Command ......................................................................................................................... 25
10.7 LRAM and LDEV Description ....................................................................................................... 82
10.8 Learn Command ........................................................................................................................... 82
11.0 DEPTH CASCADING ................................................................................................................... 84
11.1 Depth Cascading up to Four Devices (One Block) ....................................................................... 84
11.2 Depth Cascading up to Fifteen Devices (Four Blocks) ................................................................. 84
11.3 Depth Cascading for a FULL Signal ............................................................................................. 85
12.0 SRAM ADDRESSING .................................................................................................................. 86
12.1 SRAM PIO Access ........................................................................................................................ 86
12.2 SRAM Read with a Table of up to Four Devices .......................................................................... 87
12.3 SRAM Read with a Table of up to Fifteen Devices ....................................................................... 89
12.4 SRAM Write with a Table of up to Four Devices .......................................................................... 90
12.5 SRAM Write with Table(s) Consisting of up to Fifteen Devices .................................................... 92
Document #: 38-02035 Rev. *E
Page 2 of 109

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