CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 9

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

3.0
The following subsections contain command (CMD) and DQ bus (command and databus), database entry, arbitration logic,
pipeline and SRAM control, and full logic descriptions.
3.1
CMD[10:0] carries the command and its associated parameters. DQ[71:0] is used for data transfer to and from the database
entries, which comprise data and mask fields that are organized as data and mask arrays. The DQ bus carries the Search data
(of the data and mask arrays and internal registers) during the Search command as well as the address and data during Read
and/or Write operations. The DQ bus can also carry address information for the transparent accesses to the external SRAMs
and/or SSRAMs.
3.2
Each database entry comprises data and mask fields. The resultant value of the entry is “1,” “0,” or “X (do not care),” depending
on the value in the data mask bit. The on-chip priority encoder selects the first matching entry in the database that is nearest to
location 0.
Document #: 38-02035 Rev. *E
Block Diagram
DQ[71:0]
CMD[10:0]
Command Bus and DQ Bus
Database Entry (Data and Mask Arrays)
Functional Description
CMDV
CLK1X/CLK2X
ACK
EOT
FULI[6:0]
CLK_MODE
PHS_L
RST_L
and PIO Access
ID[4:1]
Command
Decode
Full Logic
Search Successful Index Registers [7:0]
Global Mask Register Pairs [15:0]
Figure 2-1. CYNSE70256 Block Diagram
Information and Command Register
Comparand Register Pairs [15:0]
[All registers are 72-bits wide.]
Next-Free Address Register
FULL
Burst Read Register
Burst Write Register
CMD
Configurable as
Configurable as
FULO[1:0]
Compare/PIO Data
128K × 72
Mask Array
Data Array
64K × 144
32K × 288
128K × 72
64K × 144
32K × 288
LHI[6:0]
BHI[2:0]
Arbitration
Logic
Bank 0
Bank 1
BHO[2:0]
SSF
SSV
LHO[1:0]
Pipeline
Control
SRAM
and
Controller
TAP
CYNSE70256
SADR[23:0]
OE_L
WE_L
CE_L
ALE_L
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TAP