CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 12

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 4-1. CYNSE70256 Signal Description (continued)
5.0
If the CLK_MODE pin is LOW, CYNSE70256 receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X
and generate an internal clock (CLK
tions.
If the CLK_MODE pin is HIGH, CYNSE70256 receives CLK1X only. CYNSE70256 uses an internal phase-lock loop (PLL) to
double the frequency of CLK1X and then divides that clock by two to generate a CLK for internal operations, as shown in
Figure 5-2.
Notes:
Document #: 38-02035 Rev. *E
Device Identification
Supplies
Test Access Port
1.
2.
3.
4.
5.
I = Input only, I/O = Input or Output, O = Output only, T = three-state output.
ACK and EOT require a weak external pulldown such as 47KΩ or 100KΩ.
Any reference to “CLK” cycles means one cycle of CLK.
“CLK” is an internal clock signal.
For the purpose of showing timing diagrams, all such diagrams in this document will be shown in CLK2X mode. For a timing diagram in CLK1X mode, the
following substitution can be made (see Figure 5-3).
Pin Name
TRST_L
Clocks
ID[4:0]
V
TCK
TDO
TMS
V
TDI
DDQ
DD
CLK2X
PHS_L
CLK
CLK1X
CLK
[4]
[4]
Type
Pin
n/a
n/a
T
I
I
I
I
I
[1]
Figure 5-1. CYNSE70256 Clocks (CLK2X and PHS_L)
[3, 4]
a depth-cascaded system starts at 0000 and goes up to 1110. 1111 is reserved for a
special broadcast address that selects all cascaded NSEs in the system. On a broadcast
Read-only, the device with the LDEV bit set to 1 responds. ID[0] stays unconnected.
Chip Core Supply
Chip I/O Supply
Test access port’s test clock.
Test access port’s test data out.
Test access port’s test mode select.
Test access port’s reset.
Device Identification. The binary-encoded device identification (ID[4:1]) for
Test access port’s test data in.
), as shown in Figure 5-1. The CYNSE70256 uses CLK2X and CLK for internal opera-
Figure 5-2. CYNSE70256 Clocks (CLK1X)
: 2.5V/3.3V.
: 1.5V.
Pin Description
[5]
CYNSE70256
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