CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 60

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The following is the sequence of operation for a single 144-bit Search command (also refer to “Command and Command
Parameters,” Section 10.2 on page 19).
The logical 144-bit Search operation is shown in Figure 10-42. The entire table of fifteen devices (consisting of 144-bit entries)
is compared against a 144-bit word K that is presented on the DQ bus in cycles A and B of the command using the GMR and
local mask bits. The GMR is the 144-bit word specified by the even and odd global mask pair selected by the GMR Index in the
command’s cycle A.
Document #: 38-02035 Rev. *E
CFG =01001010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: |LHO[1:0] is logical “or” of LHO[0] and LHO[1].
• Cycle A: The host ASIC drives CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. {CMD[10],CMD[5:3]}
• Cycle B: The host ASIC continues to drive CMDV HIGH and to apply Search command code (10) on CMD[1:0]. CMD[5:2]
signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with
the bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72-bit data ([143:72])
in order to be compared against all even locations. The CMD[2] signal must be driven to logic 0.
must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ bus during cycles
A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
entry and the hit flag (see page 14 for the description of SSR[0:7]). The DQ[71:0] is driven with 72-bit data ([71:0]) to be
compared against all odd locations.
Figure 10-41. Timing Diagram for Device Number 2 in Block Number 3 (Device 14 in a Depth-Cascaded Table)
SADR[23:0]
CMD[10:2]
I(BHI[2:0])
|(LHI[6:0])
|LHO[1:0]
CMD[1:0]
BHO[2:0]
CLK2X
PHS_L
CMDV
ALE_L
WE_L
OE_L
CE_L
SSV
DQ
SSF
0
0
1
0
0
0
0
0
0
0
cycle
Search1
A B A B A B A B
1
A B A B A B A B
01
D1
cycle
Search2
2
01
D2
cycle
Search3
3
01
D3
cycle
4
Search4
01
D4
cycle
5
cycle
6
cycle
(Hit on some
device above.)
7
Search1
cycle
8
z
z
z
z
cycle
(Hit on some
device above.)
Search2
9
Search3
(Hit on some
device above.)
z
z
cycle
10
0
0
1
1
0
Search4
(Global miss; this
device is default driver.)
CYNSE70256
Page 60 of 109