CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 23

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

locations. A single-location Write is a three-cycle operation, as shown in Figure 10-3. The burst Write adds one extra cycle for
each successive location Write.
The following is the Write operation sequence. Table 10-7 shows the Write address format for the data array, the mask array, or
single-Write SRAM. Table 10-8 shows the Write address format for the internal registers.
At the termination of cycle 3, another operation can begin.
Table 10-7. Write Address Format for Data Array, Mask Array, or SRAM (Single Write)
Table 10-8. Write Address Format for Internal Registers
Document #: 38-02035 Rev. *E
Notes:
Reserved 0: Direct
Reserved 0: Direct
Reserved 0: Direct
13. The latency of the SRAM Write will be different than the one described above (see Subsection 12.1, “SRAM PIO Access,” on page 86).
14. “ | ” stands for logical OR operation. “{}” stands for concatenation operator.
• Cycle 1A: The host ASIC applies the Write instruction to CMD[1:0] (CMD[2] = 0) using CMDV = 1, and the address supplied
• Cycle 1B:The host ASIC continues to apply the Write instruction to CMD[1:0] (CMD[2] = 0) using CMDV = 1, and the address
• Cycle 2: The host ASIC drives DQ[71:0] with the data to be written to the data array, mask array, or register location of the
• Cycle 3: Idle cycle.
[71:30]
on the DQ bus. The host ASIC also supplies the GMR index to mask the Write to the data or mask array location on {CMD[10],
CMD[5:3]}. For SRAM Writes, the host ASIC must supply the SADR[23:21] on CMD[8:6]. The host ASIC sets CMD[9] to 0 for
a normal Write.
supplied on the DQ bus. The host ASIC continues to supply the GMR index to mask the Write to the data or mask array
locations in {CMD[10], CMD[5:3]}. The host ASIC selects the device where ID[4:1] matches the DQ[25:22] lines and the bank
within the device using value on DQ[21], or it selects both banks of all the devices when DQ[25:21] = 11111.
selected device.
DQ
DQ[71:26]
Reserved
1: Indirect
1: Indirect
1: Indirect
[29]
DQ
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
CMDV
if DQ[29] is
if DQ[29] is
if DQ[29] is
(applicable
(applicable
(applicable
DQ
indirect)
indirect)
indirect)
[28:26]
DQ[25:22]
SSR
SSR
SSR
DQ
ID
cycle 0
[25:22]
DQ
ID
ID
ID
Bank 0 or 1
Figure 10-3. Single Write Cycle Timing
DQ[21]
0 or 1
0 or 1
0 or 1
Bank
Bank
Bank
[21]
DQ
A
cycle 1
Address
Write
01: Mask Array Reserved If DQ[29] is 0, this field carries the address of
00: Data Array
10: External
[20:19]
SRAM
[13]
B
DQ
11: Register
DQ[20:19]
cycle 2
Data
Reserved If DQ[29] is 0, this field carries the address of
Reserved If DQ[29] is 0, this field carries the address of
[18:16]
DQ
the data array location.
If DQ[29] is 1, the SSR specified on
DQ[28:26] is used to generate the address of
data array location: {SSR[15:2], SSR[1] |
DQ[1], SSR[0] | DQ[0]}.
the mask array location.
If DQ[29] is 1, the SSR specified on
DQ[28:26] is used to generate the address of
the mask array location: {SSR[15:2], SSR[1]
| DQ[1], SSR[0] | DQ[0]}.
the SRAM location.
If DQ[29] is 1, the SSR specified on
DQ[28:26] is used to generate the address of
SRAM location: {SSR[15:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]}.
DQ[18:7]
Reserved
cycle 3
X
cycle 4
[14]
[15:0]
DQ
Register address
CYNSE70256
[14]
[14]
DQ[6:0]
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