CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 28

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The following is the sequence of operation for a single 72-bit Search command (also refer to Subsection 10.2, “Commands and
Command Parameters,” on page 19).
Note
even and odd pairs of GMRs selected for the comparison must be programmed with the same value.
The logical 72-bit Search operation is shown in Figure 10-9. The entire table of 72-bit entries (four devices) is compared to a
72-bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and local mask bits. The effective
GMR is the 72-bit word specified by the identical value in both even and odd GMR pairs, in each of two banks of the four devices,
and selected by the GMR Index in the command’s cycle A. The 72-bit word K (presented on the DQ bus in both cycles A and B
of the command) is also stored in both even and odd comparand register pairs (selected by the comparand register index in
Document #: 38-02035 Rev. *E
CFG = 0000000000000000, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: |LHO[1:0] is logical “or” of LHO[0] and LHO[1].
• Cycle A: The host ASIC drives CMDV HIGH and applies Search command code (10) to CMD[1:0] signals. {CMD[10],CMD[5:3]}
• Cycle B: The host ASIC continues to drive CMDV HIGH and to apply Search command code (10) on CMD[1:0]. CMD[5:2]
signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with
the same bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72-bit data to
be compared. The CMD[2] signal must be driven to logic 0.
must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ bus during cycles
A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
entry and hit flag (see page 14 for a description of SSR[0:7]). The DQ[71:0] continues to carry the 72-bit data to be compared.
. For 72-bit searches, the host ASIC must supply the same 72-bit data on DQ[71:0] during both cycles A and B. Also, the
SADR[23:0]
CMD[10:2]
|(LHI[6:0])
CMD[1:0]
|LHO[1:0]
CLK2X
PHS_L
ALE_L
CMDV
WE_L
OE_L
CE_L
Figure 10-8. Timing Diagram for 72-bit Search Device Number 3 (Last Device)
SSV
SSF
DQ
0
0
0
0
1
0
cycle
Search1
1
A B A B A B A B
D1
01
cycle
Search2
2
D2
01
cycle
Search3
3
D3
01
cycle
4
Search4
D4
01
cycle
5
cycle
6
cycle
7
z
z
Search1
(Miss on
this device.)
z
z
cycle
8
Search2
(Miss on
this device.)
cycle
9
A4
z
z
Search3
(Local
winner but
not global
winner.)
cycle
10
0
1
0
Search4
(Global
winner.)
CYNSE70256
1
1
0
0
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