PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 145

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PEB20534H-10V2.1

Manufacturer Part Number
PEB20534H-10V2.1
Description
Communication Controller 208-Pin FQFP
Manufacturer
Infineon Technologies
Datasheets

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7.4.1.5
Separate, externally generated receive and transmit clocks are supplied via pins RxClk
and TxClk. In addition separate receive and transmit clock gating signals are supplied
via pins RCG and TCG. These gating signals work on a per bit basis.
Note: Clock mode 4 can only be applied in combination with High Speed Serial Mode
Note: For correct operation only HDLC Address Mode 0, PPP and Extended
Figure 46
Data Sheet
(register CCR0 bit HS =’1’). This setting optimizes the internal signal and clock
trees for high speed timing requirements.
Transparent Mode should be used.
Clock Mode 4 (High Speed Interface Clock Mode)
clock mode 4
Clock Mode 4 (High Speed) Configuration
TxCLKout
RxCLK
TxCLK
RCG
RxD
TCG
TxD
Ctrl.
Ctrl.
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
Serial Communication Controller (SCC) Cores
145
1 clock
delay
transmit clock gate signal
receive clock gate signal
tx clock out signal
signal
delay
clock supply
2
1
PEB 20534
PEF 20534
2000-05-30

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