PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 75

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

The following figure provides an example how a receive descriptor and its associated
data buffer is located in the memory as a result of a memory dump.
Figure 16
Data Sheet
DSCC4 register CH0BRDA:
Base Receive Descriptor Address Channel 0
31
31
Next Receive Descriptor Ptr.=0x30001014
Frame End Descriptor Ptr.=0x30001000
0 0
1 1 0 0
04
00
00
00
Receive Data Pointer=0x40000020
0
CH0BRDA = 0x30001000
0
written by
CPU
written by
DSCC4
0x006
0x010
03
00
00
00
Receive Descriptor Memory Example
0x00
02
A2
00
00
0x0000
0x00
01
05
00
00
0
0
75
0
Hold HI
HI
DMA Controller and Central FIFOs
Host Memory Dump:
Value:
31
0xC0060000
0x0000A205
0x00100000
0x30001014
0x40000020
0x30001000
0x04030201
0x00000000
PEB 20534
0
PEF 20534
Address:
0x30001000
0x30001004
0x30001008
0x3000100C
0x30001010
0x30001014
0x40000020
0x40000024
0x40000028
0x40000030
2000-05-30