PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 159

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

7.6
Any channel of the DSCC4 may be configured for operation at data rates up to 52 MBit/
s. To configure one SCC for high speed operation, bit ’HS’ in register CCR0 has to be
set (allows data rates above 10 MBit/s) and clock mode 4 has to be selected to configure
the internal clock unit appropriately.
The protocols supported at this high data rate are limited to HDLC address mode 0, PPP
and extended transparent mode (PPP modes up to 45 MBit/s).
The high speed mode will operate with clocks provided on TxCLK (transmitter) and
RxCLK (receiver). Clock gating is supplied on TCG and RCG pins to allow external
transceivers (HSSI, DS3, etc.) to enable/disable frame/block bursts. When the clock
gating signals are active, the SCC will not latch data from pin RxD nor will it output data
on pin TxD (idle ’1’ is transmitted when TCG is active).
Beside clock gating via signals TCG/RCG, clock gapping is also supported in high speed
mode.
In transmit direction one clock delay is inserted between detecting an active transmit
gate signal TCG and the first transmit data bit driven to the line.
A transmit clock which is in phase to the data bits on pin TxD can be provided on pin RTS
by setting bit ’TxCLKO’ in register CCR1.
Depending on the expected data traffic the user can select appropriate depth for the
central transmit FIFO. In addition a second transmit FIFO threshold (register FIFOCR4)
controls data transfer to the SCC to prevent data underrun conditions when a new frame
is started.
The central receive FIFO is allocated dynamically by the SCC as the data are received
on the serial line.
7.7
Beside the point-to-point configuration, the SCC effectively supports point-to-multipoint
(pt-mpt, or bus) configurations by means of internal idle and collision detection/collision
resolution methods.
In a pt-mpt configuration, comprising a central station (master) and several peripheral
stations (slaves), or in a multimaster configuration, data transmission can be initiated by
each station over a common transmit line (bus). In case more than one station attempts
to transmit data simultaneously (collision), the bus has to be assigned to only one
station.
– In HDLC/SDLC mode, a collision-resolution procedure is implemented by the SCC.
– In BISYNC mode, the collision-resolution is implemented by the microprocessor.
Data Sheet
Bus assignment is based on a priority mechanism with rotating priorities. This allows
each station a bus access within a predetermined maximum time delay (deterministic
CSMA/CD), no matter how many transmitters are connected to the serial bus.
High Speed Channel Operation (PEB 20534H-52 only)
Serial Bus Configuration Mode
Serial Communication Controller (SCC) Cores
159
PEB 20534
PEF 20534
2000-05-30