PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 60
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PEB20534H-10V2.1
Manufacturer Part Number
PEB20534H-10V2.1
Description
Communication Controller 208-Pin FQFP
Manufacturer
Infineon Technologies
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Data Sheet
0044
0048
004C
0034
(DMA channel specific registers)
Ch0
0014
0024
0050
0054
0058
0098
00C8
H
H
H
H
H
H
H
H
H
H
H
Ch1
0018
0028
005C
0060
0064
009C
00CC
H
H
H
H
H
H
H
Ch2
001C
002C
0068
006C
0070
00A0
00D0
H
H
H
H
H
H
H
Ch3
0020
0030
0074
0078
007C
00A4
00D4
H
H
H
H
H
H
H
FIFOCR1
FIFOCR2
FIFOCR3
FIFOCR4
(i=0..3)
IQSCCiRX
BAR
IQSCCiTX
BAR
CHiCFG
CHiBRDA
CHiBTDA
CHiFRDA
CHiLRDA
60
FIFO Control Register 1
(Transmit FIFO partition size,
distinguished for 4 transmit channels)
(see
FIFO Control Register 2
(Transmit FIFO refill threshold,
distinguished for 4 transmit channels)
(see
FIFO Control Register 3
(Receive FIFO threshold,
common to all receive channels)
(see
FIFO Control Register 4
(Transmit FIFO forward threshold,
distinguished for 4 transmit channels)
(see
Interrupt Queue Receive SCCi Base
Address
(see
Interrupt Queue Transmit SCCi Base
Address
(see
Channel i Configuration Register
(see
Channel i Base Receive Descriptor
Address
(see
Channel i Base Transmit Descriptor
Address
(see
Channel i First Receive Descriptor
Address
(see
Channel i Last Receive Descriptor
Address
(see
DMA Controller and Central FIFOs
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PEB 20534
PEF 20534
2000-05-30
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