PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 57

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

PEB 20534
PEF 20534
DMA Controller and Central FIFOs
5
DMA Controller and Central FIFOs
The DSCC4 has an 8-channel flexible DMA controller to perform data transfer with
minimal host CPU intervention and high bus efficiency between the DSCC4 and
memory.
These DMA channels service receive and transmit FIFOs of the four serial
communication controllers (SCCs) transferring data into or out of the central DMA
Controller FIFOs.
On the host system side each DMA channel transfers data either from the central receive
FIFO to the shared memory (receive direction) or from the shared memory to the central
transmit FIFO (transmit direction).
8 DMA channels, each corresponding to an individual SCC transmit or receive, operate
on linked lists in the host memory.
A ninth DMA channel transfers interrupt vectors from the central interrupt FIFO to one of
10 interrupt vector queues located in the shared host memory.
Figure 11
shows the block diagram of the DMA Controller.
Data Sheet
57
2000-05-30