PEF 24470 H V1.3 Infineon Technologies, PEF 24470 H V1.3 Datasheet
PEF 24470 H V1.3
Specifications of PEF 24470 H V1.3
SP000007617
Related parts for PEF 24470 H V1.3
PEF 24470 H V1.3 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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... Added Chapter, 7.5“Hardware Reset Timing” 115 Table 32 updated. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com 2001-11-20 updated, added Figure 9 and Chapter 3.7.2 ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.1 Local Bus Interface (PCM ...
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Table of Contents 6.10.4 Establish Subchannel Broadcast Connection . . . . . . . . . . . . . . . . . . . . 94 6.10.5 Establish Multipoint Connection . . . . . . . ...
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List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Table Table 1 Who should read what ...
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PRELIMINARY Preface The Switching IC (SWITI family of switching devices for a wide area of telecommunication and data communication applications. This document provides complete reference information according to chip interfaces, programming, internal architecture and applications. Organization of this ...
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PRELIMINARY Table 1 Who should read what? Addressed Person Programmer Board Designer Preliminary Data Sheet PEF 20450 / 20470 / 24470 Relevant Chapters 2001-11-20 ...
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PRELIMINARY 1 Overview The new switching family, called SWITI, provides a complete and cost-effective solution for all switching systems. The family is divided in two sub-families, the MTSI family and the HTSI family. The Preliminary Data Sheet describes the functionality ...
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PRELIMINARY Table 2 SWITI Family Tree (cont’d) Name Package HTSI (H-Mode) P-BGA-217-1 HTSI (M-Mode) MTSI-XL P-MQFP-100-2 PEF 24470 MTSI-L P-MQFP-100-2 PEF 20470 MTSI P-MQFP-100-2 PEF 20450 Preliminary Data Sheet PEF 20450 / 20470 / 24470 Sales Connec- Local bus code ...
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PRELIMINARY Switching IC SWITI Version 1.3 1.1 Overview of Features General • Switching capacity of 512, 1024 2048 connections of different types between different buses • Programmable data 4.096 Mbit/s, 8.192 Mbit/s, and 16.384 Mbit/s on per ...
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PRELIMINARY 1.2 Features in Detail Flexible Data Rates Each input and each output line of the local bus is programmable to operate at different data rates. The possible data rates are 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, and 16.384 Mbit/s. ...
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PRELIMINARY Broadcast With this feature it is possible to distribute one incoming time-slot to different output time- slots. Multipoint Multipoint connections can be seen as the opposite of broadcast connections. Here it is possible to generate one output time-slot consisting ...
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PRELIMINARY reduces the number of write cycles required to configure a connection from 7 (in case of 8-bit µP interface write cycles. Input/Output Tolerance The MTSI can be used environment. Inputs and outputs are ...
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PRELIMINARY IN[15:0] PFS PD C TRST TCK TDO D[7:0] A[4:0] Figure 1 Logic Symbol Preliminary Data Sheet TSI PEF 20450/20470/24470 IREQ RESET ...
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PRELIMINARY 1.4 Standard PBX or CO Application The MTSI or the HTSI in M-Mode can be used, just as the MTSC or MTSL, in standard private branch exchange or central office applications network. PBX or CO Line Unit SLMD Subscriber ...
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PRELIMINARY 2 Pin Description The pin description gives an overview of the pin numbers, names, direction, position and function ordered by the different interfaces. Note: All unused input or I/O pins should be connected to V current. 2.1 Pin Diagrams ...
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PRELIMINARY 2.2 Pin Definitions and Functions 2.2.1 Local Bus Interface (PCM) Table 3 Local Bus Interface Pin No. Symbol In (I) Out (O) 56 PFS I/O 57 PDC I/O 1) 100-97, IN[15:0] I 94-83 2) 31-37, OUT[15:0] O 40-48 1) ...
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PRELIMINARY Table 5 Clock Pins (cont’d) Pin No. Symbol In (I) Out (O) 67 NTWK_1 I 66 NTWK_2 GPCLK7 GPCLK6 GPCLK5.. 2.2.4 JTAG Interface Table 6 JTAG Interface Pin No. Symbol In ...
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PRELIMINARY Table 7 Microprocessor Interface (cont’d) Pin No. Symbol In (I) Out ( R/W 5 ALE I 61 MODE16 I 63 IREQ/ O IREQ OD 1) 10-6 A[4: 20-17, D[7:0] I/O 14-11 62 RESET I ...
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PRELIMINARY 3 Architectural Description The following sections give a short overview of the functionality of the SWITI. 3.1 Functional Block Diagram itching Factory Line tro ...
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PRELIMINARY 3.2 Overview of Functional Blocks Switching Factory The switching factory is responsible for transferring and handling the incoming data streams to the assigned output channels and time-slots. The block includes a 512, 1024, or 2048 byte input and output ...
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PRELIMINARY 3.3 Switching Factory As shown in Figure 4 the switching factory comprises the input/output data memory and the input/output data handler with the programmed connections. The I/O controller handles all lines operating at the same or different data rate. ...
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PRELIMINARY 3.3.1.4 Broadcast Switching Broadcast switching allows to distribute one incoming time-slot to different output time- slots. The input and output mechanism is the same as the normal constant delay connection mode with subchannel switching. Minimum delay is also supported ...
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PRELIMINARY TS 10 Port 0 Local Bus TS 20 Port 1 Local Bus Issued Command SPA = 0 ITSA = A DPA = 1 OTSA = 14 CCMD = Port 0 Figure 5 Bidirectional Mode 3.3.1.6 Message ...
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PRELIMINARY The internal S/P-converter is bypassed. The 8 bit data stream per time-slot is distributed on 8 data lines, one bit for every line. The least significant bit is assigned to line 0 and the most significant bit is assigned ...
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... Therefore a software reset must be issued and the device must be programmed again, except the clock configuration. Infineon Technologies provides a software driver to recalculate the chain and to recover the current connections. 3.4 Clock Generator and PLL 3 ...
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PRELIMINARY The digital PLL synchronizes the external crystal or oscillator to the selected reference clock. The digital PLL (DPLL) will be bypassed if the selected reference signal is >= 2.048 MHz. The input signal for the analog PLL (APLL) is ...
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PRELIMINARY 3.4.2.1 Functional Description fref frequency detector fref phase/ fin frequency detector Timer Figure 7 Block Diagram of APLL The value of the output frequency depends of the programming of the n-divider. The chosen output frequency for the SWITI is ...
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PRELIMINARY The digital PLL is enabled after reset or power up and is disabled after 750 µs (lock time of PLL). The counter keeps its value and the DAC output current irough is constant until the digital PLL is reseted. ...
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PRELIMINARY 3.4.2.2 Jitter Transfer Function Jitter transfers or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various ...
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PRELIMINARY 3.4.3 Phase Alignment If the phase alignment function is enabled all PLL output signal and the main divider are edge synchronized with the PLL clock input. If the selected reference signal is less than 2.048 MHz the edge synchronization ...
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PRELIMINARY 3.4.4 PLL Synchronization The PLL reference source can be selected from the primary reference master source (PFS, PDC, NTWK_1/_2). If the selected reference signal is less than 2.048 MHz the main digital PLL is used to synchronize the analog ...
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PRELIMINARY 3.7 Power-On and Reset Behavior 3.7.1 Hardware Reset There are two independent low active reset pins: RESET and TRST. If the RESET pin is activated, it immediately sets all outputs and I/O ports into tri-state, except the ECLKO pin. ...
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PRELIMINARY 4 Description of Interfaces 4.1 Local Bus Interface (PCM) The local bus is a PCM interface consisting of input and output data lines (IN, OUT), a PCM data clock PDC and a frame synchronization signal PFS. PFS PDC IN ...
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PRELIMINARY PFS 0 D ata R ate of Selected Line Input 0 O ffset of TS0 Input 1 O ffset of TS0 O utputs O ffset of TS0 Figure 11 PCM Bit Shifting For each PCM input line the offset ...
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PRELIMINARY 4.3 Microprocessor Interface A standard 8-bit multiplexed or non-multiplexed µP interface is provided compatible to Intel/Siemens (e.g. 80386EX, C166) or Motorola (e.g. 68040, 68340, 68360, 801) bus systems. If the GPIO port is not needed it can ...
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PRELIMINARY Multiplexed Mode µP AD ALE De-multiplexed Mode µ Figure 12 Multiplexed and in De-multiplexed Bus Mode Note: In both modes only the 5 LSBs of A-bus or AD/bus are connected to the Address inputs. Preliminary Data Sheet ...
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PRELIMINARY 4.4 General Purpose Port (GPIO) This port consists of 8 lines each one configurable as input or output. A change on an input line may cause an interrupt (if not masked). The user has access to the port configuration ...
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PRELIMINARY 4.5.1 Frame Group Outputs Via 8 output lines it is possible to provide 8 different framing signals which are used for synchronization purpose. All signals have a period of 125 µs. Their offset can be programmed individually within the ...
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PRELIMINARY 4.6 JTAG (Boundary Scan) The SWITI provides a fully IEEE 1149.1 compatible boundary scan support consisting of: – a complete boundary scan chain – a Test Access Port controller (TAP controller) – five dedicated pins: TCK, TMS, TDI, TDO ...
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PRELIMINARY 4.6.3 TAP Controller The Test Access Port (TAP) controller implements the state machine defined in the JTAG standard IEEE 1149.1. Transitions on the pin TMS cause the TAP controller to perform a state change. The possible instructions are listed ...
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PRELIMINARY register. This data become effective at the outputs only if an instruction has been activated that sets the BSc register to test mode: e.g. EXTEST or CLAMP. IDCODE The 32-bit identification register is serially read out via TDO. It ...
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PRELIMINARY 4.7 Identification Code via µP Read Access The SWITI offers two possibilities to read the identification code. – via the JTAG port as described in – or via the processor interface After a hardware reset the identification code is ...
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PRELIMINARY 5 Register Description The register description gives information about all registers accessible via the microprocessor interface according to address, short name, access, reset value and value range. Preliminary Data Sheet PEF 20450 / 20470 / 24470 Register Description 39 ...
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PRELIMINARY 5.1 Register Overview For 8-Bit Interface Table 12 Register Overview For 8-Bit Interface Reg Access 8-bit Name Address SPA RD/ ITSA RD/ DPA RD/ OTSA RD/ SCA RD/ GI1 ...
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PRELIMINARY Table 13 Value Range for SPA/DPA Addressed Lines Local bus input lines Table 14 Value Range for ITSA/OTSA Data Rate Number of available time-slots (Bit7..0) 2.048 Mbit/s 31..0 4.096 Mbit/s 63..0 8.192 Mbit/s 127..0 16.384 Mbit/s 255..0 Table 15 ...
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PRELIMINARY 5.2 Detailed Register Description For 8-bit Interface Source Port Address Register Reset value: 00H 7 6 SPA 0 0 BIT7..4 Must be set to 0 PA3..0 Port Address Input Time-Slot Address Register Reset value: 00H 7 6 ITSA TSA7 ...
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PRELIMINARY Output Time-Slot Address Register Reset value: 00H 7 6 OTSA TSA7 TSA6 TSA7..0 Time-Slot Address Subchannel Address Register Reset value: 00H 7 6 SCA 0 0 OSCA2..0 Output Subchannel Address ISCA2..0 Input Subchannel Address Preliminary Data Sheet RD/WR 5 ...
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PRELIMINARY General Input Register 1 Reset value: 00H 7 6 GI1 GV7 GV6 GV7..0 General Value In case of a PLL Reference Selection Command (CMD1) the content of this register is interpreted as follows: GV2..0 Clock Frequency 000 = 8 ...
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PRELIMINARY In case of the GPCLK as Frame Signal Command (CMD2) the content of this register is interpreted as follows: GV7..2 Offset within the PFS frame in number of 16.384 MHz clock cycles (lower 6 bits; refer to GI2 for ...
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PRELIMINARY General Input Register 2 Reset value: 00H 7 6 GI2 GV7 GV6 GV7..0 General Value In case of the GPCLK as Frame Signal Command (CMD2) the content of this register is interpreted as follows: GV7..5 Width of the pulse ...
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PRELIMINARY Connection Command Register Reset value: 00H 7 6 CCMD I3 I2 CC3..0 Command Code 0000 = no operation at all 0001 = Constant Delay Connection Command (incl. Broadcast Connection) (SPA, ITSA, DPA, OTSA, SCA are considered) I1..0 0010 = ...
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PRELIMINARY 1000 = Disconnect All Command 1001 = Bidirectional Connect Command (SPA, ITSA, DPA, OTSA are considered) I0 1010 = Memory Dump (Connection and Data Memory) I0 Preliminary Data Sheet Delay MODE 0 = Minimum Delay 1 = Constant Delay ...
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PRELIMINARY Configuration Command Register 1 Reset value: 00H 7 6 CMD1 I3 I2 CC3..0 Command Code 0000 = no operation 0001 = not used 0010 = PLL Reference Selection Command (GI1 is considered to set the frequency) I3..0 Synchronization Information ...
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PRELIMINARY 100 = I3 Direction Information 0111 = not used 1000 = not used 1001 = not used 1010 = Phase Alignment I2..0 must be set to 000 I3 PLL Phase Alignment (Please see description, 0 ...
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PRELIMINARY 1111 = Bit Shift Command (GI1 is considered to set shift value) (Default: Bit Shift is inactive) I1..0 Direction Control Preliminary Data Sheet PEF 20450 / 20470 / 24470 Set shift ...
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PRELIMINARY Configuration Command Register 2 Reset value: 00H 7 6 CMD2 I3 I2 CC3..0 Command Code 0000 = no operation at all 0001 = External Frequency (Must be programmed first Preliminary Data Sheet RD/ ...
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PRELIMINARY 0010 = Parallel Mode Set the first 8 local bus input lines as 8 parallel input lines and set the first 8 local bus output lines as 8 parallel output lines. I0 0011 = IREQ Pin Command I1..0 I2 ...
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PRELIMINARY I3 0111 = GPCLK as Clock Signal Command (GI1 is considered to set the frequency) (Default: All GPCLK’s are tristated) I2..0 1000 = Set Range of Data Rate Command To avoid loss of data this command should be issued ...
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PRELIMINARY 1010 = Read GPCLK Configuration I2..0 1011 = Read Local Bus (PCM) Line Configuration I0 1100 = not used 1101 = Read Bit Shift Configuration I0 1110 = not used 1111 = Software Reset I0 Preliminary Data Sheet 1110 ...
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PRELIMINARY Message Value Register Reset value: 00H MV7 MV6 MV7..0 Message Value Preliminary Data Sheet RD/ MV5 MV4 MV3 56 PEF 20450 / 20470 / 24470 Register Description Address: 0CH MV2 ...
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PRELIMINARY Interrupt Status Register 1 Reset value: 00H 7 6 ISTA1 APLL 0 APLL APLL lock indication 0 = PLL is not locked = bypassed 1 = PLL is locked ER2 Error2 Interrupt Change Indication (not active in 16-bit mode) ...
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PRELIMINARY Interrupt Error Status Register 1 Reset value: 00H 7 6 IESTA1 0 0 NW2 NTWK_2 Failure Indication NW1 NTWK_1 Failure Indication for all these status bits the values can failure detected 1 = failure detected ...
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PRELIMINARY Interrupt Mask Register 1 Reset value: 3DH 7 6 INTM1 0 0 ER2 Error2 Interrupt Change Indication Mask (not active in 16-bit mode not mask the Change Indication Bit 1 = Mask the Change Indication Bit ...
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PRELIMINARY Interrupt Error Mask Register 1 Reset value: 3FH 7 6 INTEM1 0 0 NW2 NTWK_2 Failure Indication Mask NW1 NTWK_1 Failure Indication Mask for all these indication bits the values can not mask this interrupt ...
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PRELIMINARY General Purpose Port Input Register RD Reset value: 00H 7 6 GPPI GPB7 GPB6 GPB7..0 General Purpose Bits General Purpose Port Output Register WR Reset value: 00H 7 6 GPPO GPB7 GPB6 GPB7..0 General Purpose Bits General Purpose Direction ...
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PRELIMINARY General Purpose Mask Register Reset value: FFH 7 6 GPM IM7 IM6 IM7..0 GPIO Interrupt Mask (bit 0 for line 0, bit 1 for line 1 ..) 0 = enable change detection 1 = disable change detection General Purpose ...
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PRELIMINARY Time-Slot Value Register Reset value: XXH 7 6 TSV TSV7 TSV6 For the Read Time-Slot Value Command the content of the TSV register is interpreted as: TSV7..0 Time-Slot Value For the Read Configuration Command the content of the TSV ...
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PRELIMINARY Parallel Mode TSV0 See I0 from Set Parallel Mode Command (page 53) IREQ Pin TSV2..0 See I1..0 from Set IREQ Pin Command (page 53) Local Bus (PCM) Standby TSV1..0 See I0 from Set Local Bus (PCM) Standby Command (page ...
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PRELIMINARY For the Read Local Bus (PCM) Line Configuration Command the content of the TSV register is interpreted as: TSV1.. case of the Read Bit Shift Configuration Command the content of ...
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PRELIMINARY Configuration Register Reset value: XXH 7 6 CON CON7 CON6 For the Memory Dump Command (CCMD) the content of the CON register is: CON7..0 Connection and Data Memory For the Read GPCLK Configuration Command the content of the CON ...
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PRELIMINARY 5.3 Register Overview For 16-Bit Interface Table 16 Register Overview For 16-Bit Interface Reg Access Address Reset Name SA RD/ RD/ RD/ CC16 RD/ CMD1 RD/WR 08H CMD2 RD/WR ...
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PRELIMINARY 5.4 Detailed Register Description For 16-Bit Interface Source Address Register Reset value: 0000H 15 14 TSA7 TSA6 High See Input Time-Slot Address Register on page Low See Source Port Address Register on page Destination ...
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PRELIMINARY General Input Register Reset value: 0000H 15 14 GV15 GV14 GV7 GV6 GV15..0 General Value GV15..8 See General Input Register 2 on page GV7..0 See General Input Register 1 on page Connection Command Register 16-bit Reset ...
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PRELIMINARY Interrupt Error Status Register Reset value: 0000H 15 14 CON PLL IESTA High See Interrupt Error Status Register 2 on page Low See Interrupt Error Status Register 1 on page Interrupt Error Mask Register Reset ...
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PRELIMINARY IDCODE Register Reset value: IDCODE 7 6 IDC IDC7 IDC6 IDC7..0 IDCODE refer to Time-Slot Value / Configuration Register RD Reset value: XXXXH 15 14 TSVC15 TSVC14 TSVC 7 6 TSVC7 TSVC6 TSVC15..8 Configuration and Connection Data Memory (refer ...
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PRELIMINARY 6 Programming the Device The register set consists of parameter registers (SPA, ITSA, SCA, DPA, OTSA, GI1..), command registers (CCMD, CMD1, CMD2) and status registers (ISTA1, IESTA1, IESTA2). Please note that some bits contained in the register Register 1) ...
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PRELIMINARY 6.1 Read and Write Access For the read and write access it is necessary to distinguish between a connection and configuration command. The connection command register is used to establish a connection (described in configure the device, e.g. set ...
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PRELIMINARY 6.2 Interrupt Handling The SWITI interrupt concept consists of four interrupt status register with their corresponding mask register. The five interrupt status register can be divided in one main register, and a sub group including two error interrupt register, ...
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PRELIMINARY Masking Interrupts If an interrupt is not masked (enabled) the IREQ pin will be active if one of the status bits in the interrupt status register is set. The mask bit prevents that the IREQ pin will be active ...
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PRELIMINARY 6.3 Command and Register Overview The following table (Table issuing an appropriate connection command. Table 17 Affected Registers for Connection Commands Command Connect/Disconnect (without subchannels) Connect (with subchannels) Disconnect (with subchannels) Send Message Stop Message Disconnect Part of Broadcast ...
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PRELIMINARY The following table (Table issuing an appropriate configuration command. Table 18 Affected Registers for Configuration Commands Command CMD1 CMD2 PLL Reference x PCM Clock Output x Phase Alignment x Set Bit Rate Local x Bus Read Time-Slot x Clock ...
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PRELIMINARY The command registers have the following structure CC3..0 is the command code and I3..0 is the parameter code. The following tables (Table 19 parameter codes and the related function. Table 19 Connection Command and Parameter ...
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PRELIMINARY Table 20 Configuration Command 1 and Parameter Codes Command Command Code (low nibble) Set Bit Rate 1) Local Bus 2) Read Time-Slot 3) Bit Shift 1) the input and output port is determined in SPA, 2) the time-slot is ...
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PRELIMINARY Table 21 Configuration Command 2 and Parameter Code (cont’d) Command Command (low nibble) Standby Local Bus Loop 1) Frame Signal 2) GPCLK as Clock Range of Data Rate 3) Read Configuration Read GPCLK 4) Configuration Read Local Bus Line ...
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PRELIMINARY 6.4 Indirect Configuration Register Access It is possible to read the current SWITI configuration with an indirect register access for analyze and test purpose. There are five commands in the used to read the configuration. The clock generator output ...
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PRELIMINARY 6.5 Initialization Procedure After the reset process the PLL, local bus (PCM) interface, and some other signals need to be initialized. Since the SWITI offers the possibility to use two different external crystal/oscillator frequencies the command ’Set external frequency’ ...
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PRELIMINARY 6.6 Clocking Unit The PCM clock signals for the line interface will be provided from external PCM devices if the SWITI is used as PCM clock slave or will be provided from the internal PLL if the SWITI is ...
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PRELIMINARY 6.7 Local Bus (PCM) Line Interface 6.7.1 Standby Command All PCM data lines are in a high impedance state after the reset process. If they are configured (data rate, bit shift) they can be enabled with the standby command. ...
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PRELIMINARY 6.7.3 Performing Bit Shifting The bit shift is performed on half-bit steps, not on a clock basis true bit shift, it means that with a data rate equals to the data clock frequency (e.g. 4.096 Mbit/s ...
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PRELIMINARY 6.7.3.2 Output Bit Shifting PFS Data Rate of Line Local-Bus O utput Lines Figure 20 Example: Output Bit Shifting Example (8-bit µP interface): Output time-slot 0 of all output lines begins with the first falling edge relative to the ...
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PRELIMINARY 6.8 Global Clock Signals 6.8.1 Framing Groups PFS 16.384 Mbit GPCLK_1 GPCLK_2 Figure 21 Example Framing Groups Example (8-bit µP interface): Frame signal on GPCLK_1 starts with the rising edge of 64th clock cycle ...
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PRELIMINARY 6.9 Read Time-Slot Value By issuing this command the time-slot value appears in the register and an interrupt will be caused and a new read time-slot value will be accepted. The command has to be issued for every read ...
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PRELIMINARY 6.10 Establish Connections The following chapter describes the programming of several kinds of connections. The programming interface allows to program or re-program a connection during the normal switching mode. Before a new connection for a specific output time-slot and ...
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PRELIMINARY 6.10.2 Subchannel Switching With the subchannel address register (SCA) and the constant delay command it is possible to program 1,2, and 4 connections. The following figure explains the relation between the subchannel address and the corresponding bits in one ...
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PRELIMINARY Example (8-bit µP interface): Connect low nibble of time-slot 10 of local bus input line 3 with high nibble of output time- slot 30 of local bus output line constant delay connection – Write 08 to ...
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PRELIMINARY Example (16-bit µP interface): – Write 0A03 – Write 1E0D – Write 1921 to CC16 H 6.10.2.3 Establish 1-bit Connections Fram e S ignal Local-Bus Input Line 3 Loca utput Line ...
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PRELIMINARY 6.10.3 Establish Broadcast Connections Fram e Signal Local-Bus Input Line 3 Local-Bus O utput Line 13 Local-Bus O utput Line 15 Figure 27 Example: Broadcast Connection Example (8-bit µP interface): Connect time-slot 10 of local bus line 3 with ...
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PRELIMINARY 6.10.4 Establish Subchannel Broadcast Connection F ram e S ignal Local-B us Input Line 3 constant delay Local utput Line 0 Figure 28 Example: Subchannel Broadcast Connection – First Connection – Write 03 to SCA H – ...
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PRELIMINARY – Write 1E to OTSA H – Write 00 to DPA H – Write 31 to CCMD H – Fifth Connection – Write 08 to SCA H – Write 0A to ITSA H – Write 03 to SPA H ...
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PRELIMINARY Example (16-bit µP interface): – Write 0A03 – Write 1E0D – Write 0007 to CC16 H – Write 1408 – Write 0007 to CC16 H 6.11 Send Messages Sending messages ...
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PRELIMINARY 6.12 Release Connections 6.12.1 Release 8-bit Connections Example (8-bit µP interface): Release connection established in – Write 0A to ITSA H – Write 03 to SPA H – Write 1E to OTSA H – Write 0D to DPA H ...
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PRELIMINARY – Write 1E to OTSA H – Write 0D to DPA H – Write 25 to CCMD H Example (16-bit µP interface): – Write 0A03 – Write 1E0D – Write 1925 to CC16 ...
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PRELIMINARY 6.12.5 Release Broadcast Connection Example (8-bit µP interface): Release connection established in a broadcast connection have to be released by the Disconnect Part of the Broadcast Command. The last connection has to be released by the Disconnect Command. – ...
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PRELIMINARY – Write 00 to DPA H – Write 26 to CCMD H – Third Connection – Write 23 to SCA H – Write 0A to ITSA H – Write 03 to SPA H – Write 1E to OTSA H ...
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PRELIMINARY 7 Timing Diagrams 7.1 PCM Interface Timing The following tables and figures give the PCM timing with a capacitive load of 50 pF. PDC and PFS are configured as inputs. The timing is also valid if PDC and PFS ...
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PRELIMINARY Table 22 PCM Timing Parameter Period PFS PFS high time PFS set up time to clock PFS hold time from clock PFS high time PFS set up time to clock PFS hold time from clock PFS high time PFS ...
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PRELIMINARY Table 22 PCM Timing (cont’d) Parameter Serial data input set up time Serial data input hold time t Serial data input set up time Serial data input hold time t Serial data input set up time Serial data input ...
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PRELIMINARY 7.2 PCM Parallel Mode Timing TIME 255 SLOT PDC PFS IN OUT Figure 32 Parallel Mode Timing Table 23 PCM Parallel Mode Timing Parameter Frame setup time to clock Frame hold time to clock Input data setup time Input ...
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PRELIMINARY 7.3 Microprocessor Interface Timing Microprocessor accesses of the SWITI are performed by an activation of the address and CS. – By driving the MODE16 pin ’low’ the user selects the 8-bit microprocessor interface, by driving it ’high’ - the ...
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PRELIMINARY . t AS A0-A4 RDxCS D0-D7 Figure 33 Infineon/Intel Read Cycle in De-Multiplexed Mode t AS A0-A4 WRxCS D0-D7 Figure 34 Infineon/Intel Write Cycle in De-Multiplexed Mode Addresses will be latched with the falling WR edge during the write ...
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PRELIMINARY Table 25 Infineon/Intel Timing in Multiplexed Mode Parameter ALE pulse width Address setup time to ALE falling edge Address hold time from ALE falling edge Address latch setup time to WR pulse width RD recovery time Data ...
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PRELIMINARY ALE WRxCS t AL AD0-AD7 Address Figure 36 Infineon/Intel Write Cycle in Multiplexed Mode 7.3.3 Motorola Microprocessor Timing In this mode R/W distinguishes between Read and Write interactions, and DS is used for timing ...
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PRELIMINARY t AS A0-A4 R/W CSxDS D0-D7 Figure 37 Motorola Read Cycle t AS A0-A4 R/W CSxDS D0-D7 Figure 38 Motorola Write Cycle Preliminary Data Sheet Address t t DSD RWD Data Address t ...
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PRELIMINARY 7.4 JTAG Interface Timing Table 27 JTAG Interface Timing Parameter Test Clock (TCK) Period Test Clock (TCK) Period Low Test Clock (TCK) Period High TMS Set-up time before TCK Rising Edge TMS Hold time after TCK Rising Edge TDI ...
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PRELIMINARY TCK TMS TDI TD0 any input any output TRST Figure 39 Boundary Scan Timing Preliminary Data Sheet PEF 20450 / 20470 / 24470 t TCJ t t CJH CJL t SUJ t DSE t ODF t IPJ t OPD ...
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PRELIMINARY 7.5 Hardware Reset Timing Table 28 Hardware Reset Timing Parameter Hardware Reset time Figure 40 Hardware Reset Timing Preliminary Data Sheet Symbol Limit Values min. typ. max RESET ...
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PRELIMINARY 8 Electrical Characteristics 8.1 Absolute Maximum Ratings Table 29 Absolute Maximum Ratings Parameter Ambient temperature under bias PEF Storage temperature Supply voltage Voltage on any input or output pin (referenced to ground) 1) ESD robustness (HBM: 1 ...
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PRELIMINARY 8.3 Crystal Oscillator The SWITI requires a 16.384 MHz or 32.768 MHz clock source. To supply this a 16.384 MHz or 32.768 MHz crystal can be connected between the ECLKI and ECLKO pins. Figure 41 shows the crystal with ...
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PRELIMINARY 8.4 DC Characteristics DC Characteristics Table 32 Parameter Input low voltage Input high voltage Output low voltage Output high voltage Typical power supply current Input leakage current Output leakage current Note: The listed characteristics are ensured over the operating ...
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PRELIMINARY 8.6 AC Characteristics Ambient temperature under bias range, VDD = 3.3 V ± Inputs are driven to 2.4 V for a logical ’1’ and to 0.4 V for a logical ’0’. Timing measurements for all other signals ...
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PRELIMINARY 9 Package Outlines P-MQFP-100-2 (Plastic Metric Quad Flat Package) Figure 43 Outlines of P-MQFP-100-2 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Preliminary Data Sheet ...
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PRELIMINARY A Analyze Memory 20 B Bidirectional Switching Boundary Scan 35, 37 Broadcast 7 Broadcast Switching 18 C Clock Shift 6 Constant Delay Data Rate Adaption 6 F Flexible Data Rates 6 Frame Group 34 Framing Group ...
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PRELIMINARY R Read Access 7 Register Configuration Command Register 1 Configuration Command Register 2 Configuration Register Connection Command Register Destination Address Register Destination Port Address Register General Input Register General Input Register 1 General Input Register 2 General Purpose Direction ...
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... Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher Published by Infineon Technologies AG ...