PEF 24470 H V1.3 Infineon Technologies, PEF 24470 H V1.3 Datasheet - Page 83

• Manufacturer Part Number: PEF 24470 H V1.3
• Description: IC MTSI-XL SWITCHING MQFP100
• Manufacturer: Infineon Technologies
• Series: SWITIr

Specifications of PEF 24470 H V1.3

• Function: Switching IC
• Interface: PCM, PLL
• Number Of Circuits: 1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 200mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-SQFP
• Includes: Clock Shift, Data Rate Adaption, Multipoint Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF24470HV1.3X; SP000007617

PRELIMINARY
6.2
The SWITI interrupt concept consists of four interrupt status register with their
corresponding mask register. The five interrupt status register can be divided in one
main register, and a sub group including two error interrupt register, one general purpose
interrupt register and one time-slot value register. Every sub register has a bit in the main
register to indicate the set of an interrupt in the assigned error or general purpose
register or to indicate a new value in the time-slot value register.
The interrupt status register can be read via the microprocessor interface. The NFC and
RDY will be set and reset from the internal controller.
When an interrupt occurs one or more of the bit GPIO, TSA, ER2, or ER1 is set, then the
assigned secondary interrupt status register or time-slot value register must be read first
in order to check for the cause of the interrupt. After a secondary status register read
access, the error status register and the corresponding bit in the Interrupt Status
Register 1 (ISTA1) will be reset.
Figure 16
The IREQ output is level active. It stays active until all interrupt sources have been
serviced. If a new status bit is set while an interrupt is being serviced (µP read access),
the IREQ pin stays active. For the duration of a write access to the
IREQ line is deactivated. When using an edge-triggered interrupt controller, it is
recommended to rewrite the
APLL, STR, RDY and NFC Bits
If the internal controller does set the RDY bit for the first time and the bit is not masked
an interrupt will be generated. If the µP reads the
deactivated. The RDY bit is still active and can be reset from the internal controller.
The NFC, STR and APLL bits are not set by any interrupt and therefore can not be
masked. Setting these bit does not generate any interrupt. The NFC bit is set from the
internal controller if no further connections can be established. The STR bit is set from
the internal stream to stream controller if a stream to stream connection is configured.
The APLL bit is set from the internal analog PLL controller if the PLL is locked.
Preliminary Data Sheet
Interrupt Handling
Interrupt Error Status R egister 2
Interrupt Error Status R egister 1
8-bit µP Access Interrupt Structure
INTM1
APLL
register at the end of any interrupt service routine.
ER2
ER 1
74
G PIO
TSA
N FC
ISTA1
R DY
PEF 20450 / 20470 / 24470
G eneral Purpose Interrupt Status R egister
M ain Status Register
register the interrupt will be
Programming the Device
Tim e Slot Value Register
INTM1
register the
sw iti_ 063 .em f
2001-11-20