PEF 24470 H V1.3 Infineon Technologies, PEF 24470 H V1.3 Datasheet - Page 45

• Manufacturer Part Number: PEF 24470 H V1.3
• Description: IC MTSI-XL SWITCHING MQFP100
• Manufacturer: Infineon Technologies
• Series: SWITIr

Specifications of PEF 24470 H V1.3

• Function: Switching IC
• Interface: PCM, PLL
• Number Of Circuits: 1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 200mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-SQFP
• Includes: Clock Shift, Data Rate Adaption, Multipoint Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF24470HV1.3X; SP000007617

PRELIMINARY
4.6.3
The Test Access Port (TAP) controller implements the state machine defined in the
JTAG standard IEEE 1149.1.
Transitions on the pin TMS cause the TAP controller to perform a state change. The
possible instructions are listed in the following table.
Table 9
The instruction length is four bit.
EXTEST is used to verify the board interconnections.
When the TAP controller is in the state “update DR”, all output pins are updated with the
falling edge of TCK. When it has entered state “capture DR” the levels of all input pins
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
INTEST supports internal chip testing.
When the TAP controller is in the state “update DR”, all inputs are updated internally with
the falling edge of TCK. When it has entered state “capture DR” the levels of all outputs
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction enables all signal pins (inputs and outputs) to be
sampled during operation (SAMPLE) and the result to be shifted out through the shift
BSc register. The function of the internal logic is not influenced by this instruction. While
shifting out, the BSc cells can be serially loaded at the same time with defined values
through TDI (PRELOAD). The SAMPLE/PRELOAD instruction selects the boundary
scan register in normal mode. In state CAPTURE-DR data is loaded into the boundary
scan register with the rising edge of TCK. In state UPDATE-DR the contents of the
boundary scan register are written into the second register stage of the boundary scan
Preliminary Data Sheet
Code
0000
0001
0100
0101
0110
0111
1111
TAP Controller
Instruction
EXTEST
IDCODE
HIGHZ
SAMPLE/PRELOAD Snap-shot testing
INTEST
CLAMP
BYPASS
TAP Controller Instructions
Function
External testing
Reading ID code
High impedance state of all boundary scan outputs
Internal testing
Reading outputs
Bypass operation
36
PEF 20450 / 20470 / 24470
Description of Interfaces
2001-11-20