PEF 24470 H V1.3 Infineon Technologies, PEF 24470 H V1.3 Datasheet - Page 25

• Manufacturer Part Number: PEF 24470 H V1.3
• Description: IC MTSI-XL SWITCHING MQFP100
• Manufacturer: Infineon Technologies
• Series: SWITIr

Specifications of PEF 24470 H V1.3

• Function: Switching IC
• Interface: PCM, PLL
• Number Of Circuits: 1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 200mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-SQFP
• Includes: Clock Shift, Data Rate Adaption, Multipoint Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF24470HV1.3X; SP000007617

PEF 20450 / 20470 / 24470
Architectural Description
PRELIMINARY
3.2
Overview of Functional Blocks
Switching Factory
The switching factory is responsible for transferring and handling the incoming data
streams to the assigned output channels and time-slots. The block includes a 512, 1024,
or 2048 byte input and output data memory as well as an input and output connection
memory.
Local bus I/O Block
The block is designed to handle the conversion of the data provided via the switching
block and the external local bus (PCM) interface. It performs the PCM timing, the data
rate selection and the tristate control.
Microprocessor Interface Block
A standard 8-bit multiplexed or de-multiplexed µP interface is provided, compatible to
Intel/Infineon Tech. (e.g. 80386EX, C166) and Motorola (e.g. 68040, 68340, 68360, 801)
bus systems. If the GPIO port is not needed it can be used to provide a 16-bit µP
interface.
GPIO Block
This block supports up to 8 external port lines each one configurable as input or output.
A change on an input line may cause an interrupt (if not masked). The user has access
to the port configuration and information via the appropriate registers of the µP interface.
PLL and Clock Block
The PLL generates all frequencies supporting the local bus (PCM). The internal phase-
locked loop (PLL) generates all bus frequencies synchronized to a selected reference
signal. The output frequency tolerance is equal to the input frequency tolerance. The PLL
operates from a 16.384 MHz, or 32.768 MHz external crystal, oscillator.
Preliminary Data Sheet
16
2001-11-20