PEF 24470 H V1.3 Infineon Technologies, PEF 24470 H V1.3 Datasheet - Page 33

• Manufacturer Part Number: PEF 24470 H V1.3
• Description: IC MTSI-XL SWITCHING MQFP100
• Manufacturer: Infineon Technologies
• Series: SWITIr

Specifications of PEF 24470 H V1.3

• Function: Switching IC
• Interface: PCM, PLL
• Number Of Circuits: 1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 200mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-SQFP
• Includes: Clock Shift, Data Rate Adaption, Multipoint Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF24470HV1.3X; SP000007617

PEF 20450 / 20470 / 24470
Architectural Description
PRELIMINARY
The digital PLL is enabled after reset or power up and is disabled after 750 µs (lock time
of PLL). The counter keeps its value and the DAC output current irough is constant until
the digital PLL is reseted.
The second order analog PLL consists of a phase/frequency detector (PFD), a charge
pump (CP), a loop filter and the CCO.
The PFD which is sensitive to the rising edge detects any phase or frequency difference
between the input clock (fref) and the divided output clock (feedback) and generates a
control signal proportional to the phase difference. The output signals up and down
cause the charge pump to modulate the amount of charge in the low pass filter (VTOI)
for the integral part (iint) and to feed current into the CCO for the proportional part
(iprop). With these two currents and the DAC output irough the CCO is controlled. If
feedback is leading fref, the oscillator is too fast. The down signal is activated and the
CP subtracts some current iprop. When fref is in phase with the feedback the PLL will
hold the control current at that level and phase lock will be achieved. Thus through this
negative feedback arrangement, the PLL causes the feedback and fref signals to be
equal with minimum phase offset. If the analog PLL becomes unstable, a signal pllko is
generated which resets the digital PLL.
Preliminary Data Sheet
24
2001-11-20