ATmega64A Atmel Corporation, ATmega64A Datasheet
ATmega64A
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ATmega64A Summary of contents
Page 1
... Global Pull-up Disable • I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega64A • Speed Grades – MHz for ATmega64A ® 8-bit Microcontroller (1) 8-bit Microcontroller with 64K Bytes In-System Programmable Flash ATmega64A 8160C– ...
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... Pin Configuration Figure 1-1. RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (ICP3/INT7) PE7 Note: 8160C–AVR–07/09 Pinout ATmega64A PEN (T3/INT6) PE6 8 9 (SS) PB0 10 (SCK) PB1 11 (MOSI) PB2 12 (MISO) PB3 13 (OC0) PB4 14 (OC1A) PB5 ...
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... Overview The ATmega64A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64A achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power con- sumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... Atmel ATmega64A is a powerful microcontroller that provides a highly-flexi- ble and cost-effective solution to many embedded control applications. The ATmega64A AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits. ...
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... As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega64A as listed on 75. 2.3.4 Port B (PB7:PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
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... As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega64A as listed on 83. 2.3.8 Port F (PF7:PF0) Port F serves as the analog inputs to the A/D Converter ...
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... PPM over 20 years at 85°C or 100 years at 25°C. 8160C–AVR–07/09 , even if the ADC is not used. If the ADC is used, it should be connected Figure 10-1 on page 52 327. PEN has no function during normal operation. 1. ATmega64A Table 28-3 on page CC and its value is given in Section 7 ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 8160C–AVR–07/09 ATmega64A 8 ...
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... This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- 8160C–AVR–07/09 Block Diagram of the AVR MCU Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega64A Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...
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... The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses which can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega64A has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
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... Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 8160C–AVR–07/ R/W R/W R/W R ⊕ V ATmega64A R/W R/W R/W R SREG 11 ...
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... Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 6-2, each register is also assigned a data memory address, mapping them ATmega64A 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... SP12 SP7 SP6 SP5 SP4 R/W R/W R/W R/W R/W R/W R/W R directly generated from the selected clock source for the CPU ATmega64A R26 (0x1A R28 (0x1C R30 (0x1E SP11 SP10 SP9 SP8 SP3 SP2 SP1 SP0 3 2 ...
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... Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back for details. ATmega64A “Memory Program- “Interrupts” on page 60. The list also “ ...
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... EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ 8160C–AVR–07/09 “Boot Loader Support – Read-While-Write Self-programming” on page ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) /* store SREG value */ ATmega64A 15 ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 8160C–AVR–07/09 ; set global interrupt enable ATmega64A 16 ...
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... AVR Memories This section describes the different memories in the ATmega64A. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega64A features an EEPROM Memory for data storage. All three memory spaces are linear and regular ...
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... Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc- tions can be used. The Extended I/O space does not exist when the ATmega64A is in the ATmega103 compatibility mode. ...
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... Register File, the next 64 location the standard I/O memory, and the next 4,000 locations address the internal data SRAM. An optional external data SRAM can be used with the ATmega64A. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM ...
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... Registers $0020 - $005F 64 I/O Registers 160 Ext I/O Reg. $0060 - $00FF $0100 Internal SRAM (4096 x 8) $10FF $1100 External SRAM (0 - 64K x 8) $FFFF ATmega64A Memory Configuration B Data Memory 32 Registers $0000 - $001F 64 I/O Registers $0020 - $005F $0060 Internal SRAM (4000 x 8) $0FFF $1000 External SRAM ...
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... EEPROM Data Memory The ATmega64A contains 2K bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... I/O Memory The I/O space definition of the ATmega64A is shown in All ATmega64A I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions ...
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... Lower Sector SRW01 SRW00 SRL[2..0] Upper Sector SRW11 SRW10 0xFFFF 1. ATmega64A in non ATmega103 compatibility mode: Memory Configuration A is available (Memory Configuration B N/A). ATmega64A in mega103 compatibility mode: Memory Configuration B is available (Memory Configuration A N/A). ATmega64A Figure 1-1 on page Table 13-21 on page 87). The memory configura- (1) Memory Configuration B ...
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... The number of bits that are assigned to address high byte are fixed. • The external memory section cannot be divided into sectors with different wait-state settings. • Bus Keeper is not available. • RD, WR, and ALE pins are output only (Port G in ATmega64A). 7.5.3 Using the External Memory Interface The interface consists of: • ...
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... The most important parameters are the access time for the external memory com- pared to the set-up requirement of the ATmega64A. The access time for the external memory is defined to be the time from receiving the chip select/address until the data of this address actu- ally is driven on the bus ...
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... Prev. Data Address DA7:0 (XMBK = SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external). ATmega64A ( Address Address XX Data ...
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... DA7:0 (XMBK = 1) Prev. Data Address RD 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal or external). ATmega64A Address Data Data Data ...
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... AVR Memory Map External 32K SRAM 0x0000 Internal Memory 0x10FF 0x1100 External 0x7FFF 0x8000 Memory 0x90FF 0x9100 (Unused) 0xFFFF ATmega64A Figure 7-10. Memory configuration B refers to the Memory Configuration B AVR Memory Map 0x0000 0x0000 Internal Memory 0x0FFF 0x1000 0x10FF 0x1100 External 0x7FFF 0x7FFF ...
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... PC7:5 for external memory ldi r16, (0<<XMM1)|(0<<XMM0) XMCRB, r16 sts ; store 0x55 to address (OFFSET + external memory ldi r16, 0x55 sts 0x0001+OFFSET, r16 (1) 1. See “About Code Examples” on page 8. ATmega64A 29 ...
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... When the entire SRAM address space is configured as one sec- tor, the wait states are configured by the SRW11 and SRW10 bits. 8160C–AVR–07/ SRE SRW10 SE R/W R – SRL2 SRL1 R R/W R ATmega64A SM1 SM0 SM2 IVSEL R/W R/W R/W R SRL0 SRW01 SRW00 SRW11 R/W R/W R/W ...
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... For further details of the timing and wait states of the External Memory Interface, see 6 to Figure 7-9 how the setting of the SRW bits affects the timing. ATmega64A Sector Limits Lower sector = N/A Upper sector = 0x1100 - 0xFFFF Lower sector = 0x1100 - 0x1FFF Upper sector = 0x2000 - 0xFFFF ...
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... EEAR7 EEAR6 EEAR5 EEAR4 R/W R/W R/W R ATmega64A – XMM2 XMM1 XMM0 R R/W R/W R Table 7-4. As described in 27 possible to use Released Port Pins None PC7 PC7 - PC6 PC7 - PC5 PC7 - PC4 PC7 - PC3 ...
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... Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATmega64A and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt ...
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... Flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 8160C–AVR–07/09 EEPROM Programming Time Number of Calibrated RC Oscillator 1. Uses 1 MHz clock, independent of CKSEL Fuse settings. ATmega64A for details about Boot Table 7-5 lists the typical pro- (1) Cycles ...
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... EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega64A 35 ...
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... Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in r16,EEDR ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; ATmega64A 36 ...
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... AVR Clock I/O Control Unit clk ASY Clock Multiplexer Timer/Counter External RC External Clock Oscillator Oscillator is halted, enabling TWI address reception in all sleep modes. I/O ATmega64A CPU Core RAM clk ADC clk CPU clk FLASH Reset Logic Watchdog Timer Source Clock Watchdog Clock Watchdog ...
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... ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. 343. Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( ATmega64A (1) CKSEL3:0 1111 - 1010 1001 1000 - 0101 0100 - 0001 0000 = 3.0V) Number of Cycles CC 4 ...
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... This option should not be used with crystals, only with ceramic resonators. ATmega64A Figure 8-2. Either a quartz crystal or a Table 8-3. For ceramic resonators, the XTAL2 XTAL1 GND Table 8-3. Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
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... Start-up Time from Additional Delay from Power-down and Power-save ( 32K CK 1. These options should only be used if frequency stability at start-up is not important for the application. ATmega64A Additional Delay from Reset (V = 5.0V) Recommended Usage CC Ceramic resonator, fast 4.1 ms rising power Ceramic resonator, slowly 65 ms ...
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... Start-up Times for the External RC Oscillator Clock Selection Start-up Time from Additional Delay from Power-down and Power-save ( This option should not be used when operating close to the maximum frequency of the device. ATmega64A XTAL2 XTAL1 GND Frequency Range (MHz) 0.1 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 Reset ( ...
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... Start-up Times for the Internal Calibrated RC Oscillator Clock Selection Start-up Time from Power- down and Power-save The device is shipped with this option selected. ATmega64A Table 8-7. If selected, it will operate with no exter- and Temperature. When this Oscillator is used CC Nominal Frequency (MHz) 1.0 2 ...
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... Start-up Time from Power- down and Power-save The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36 pF. ATmega64A Additional Delay from Reset (V = 5.0V) Recommended Usage CC – BOD enabled 4 ...
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... Source clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter0 registers may fail. ( CAL7 CAL6 CAL5 R/W R/W R/W Device Specific Calibration Value 1. The OSCCAL Register is not available in ATmega103 compatibility mode. ATmega64A XDIV4 XDIV3 XDIV2 XDIV1 R/W R/W R/W R ...
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... Oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 8-10. OSCCAL Value 8160C–AVR–07/09 Table 8-10. Internal RC Oscillator Frequency Range Min Frequency in Percentage of Nominal Frequency (%) 0x00 50 0x7F 75 0xFF 100 ATmega64A Max Frequency in Percentage of Nominal Frequency (%) 100 150 200 45 ...
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... SPM/EEPROM ready interrupt, an external level interrupt on INT7: External Interrupt on INT3:0 can wake up the MCU from ADC Noise Reduction mode. 8160C–AVR–07/09 presents the different clock systems in the ATmega64A, and their distri- and clk , while allowing the other clocks to run. ...
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... SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. 8160C–AVR–07/09 ATmega64A “8-bit Timer/Counter0 with PWM for details. “Clock Sources” on page 38 ...
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... Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and 8160C–AVR–07/09 Oscillators ( ( (2) ( (2) ( “Analog Comparator” on page 230 ATmega64A Wake Up Sources ( ( ( (3) (2) ...
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... Watchdog Timer. ) and the ADC clock (clk I/O “Digital Input Enable and Sleep Modes” on page 72 /2, the input buffer will use excessive power. CC ATmega64A for details on how to “Internal Voltage Refer- ) are stopped, the input buffers of the ADC for ...
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... Standby mode and Extended Standby mode are only available with external crystals or resonators. ATmega64A SM1 SM0 SM2 IVSEL R/W R/W R/W R Table 9-2. Sleep Mode Idle ADC Noise Reduction Power-down ...
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... Reset Sources The ATmega64A has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
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... Clock Generator CKSEL[3:0] SUT[1:0] Table 28-3. The POR is activated whenever V rise. The RESET signal is activated again, without any delay, CC decreases below the detection level. CC ATmega64A DATA BUS MCU Control and Status Register (MCUCSR) Brown-Out Delay Counters CK TIMEOUT is below the detection level. The CC ...
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... V POT RST RESET t TOUT RESET V POT V CC RESET RESET Table 28-3) will generate a reset, even if the clock is not running. on its positive edge, the delay counter starts the MCU after the RST has expired. TOUT CC ATmega64A CC V RST t TOUT 53 ...
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... Brown-out Detection ATmega64A has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike free Brown-out Detection. The ...
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... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega64A resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to ...
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... Level State Unprogrammed 1 Disabled Programmed 2 Enabled Unprogrammed 0 Disabled Programmed 2 Enabled WATCHDOG OSCILLATOR page 57 ATmega64A How to Disable How to Change the WDT Time-out Timed Timed sequence sequence Always enabled Timed sequence Timed No restriction sequence Always enabled Timed sequence (WDE bit description) must be followed. 56 ...
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... JTD – – R Only EXTRF and PORF are available in mega103 compatibility mode – – – ATmega64A JTRF WDRF BORF EXTRF R/W R/W R/W R/W See Bit Description WDCE WDE WDP2 WDP1 R/W R/W R/W R/W 0 ...
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... Bits 7:5 – Res: Reserved Bits These bits are reserved bits in the ATmega64A and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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... Write logical one to WDCE and WDE ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret /* Reset WDT*/ _WDRC(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; ATmega64A 59 ...
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... Interrupts 11.1 Overview This section describes the specifics of the interrupt handling as performed in ATmega64A. For a general explanation of the AVR interrupt handling, refer to page 14. 11.2 Interrupt Vectors in ATmega64A Table 11-1. Vector No 8160C–AVR–07/09 ...
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... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 11-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega64A is: Address Labels Code 0x0000 0x0002 0x0004 0x0006 ...
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... Enable interrupts <instr> xxx :. :. :. Comments r16,high(RAMEND); Main program start out SPH,r16 ; Set Stack Pointer to top of RAM ldi r16,low(RAMEND) out SPL,r16 sei ; Enable interrupts <instr> xxx jmp EXT_INT0 ; IRQ0 Handler jmp EXT_INT1 ; IRQ1 Handler :. :. ; jmp SPM_RDY ; Store Program Memory Ready Handler ATmega64A 62 ...
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... Comments jmp RESET ; Reset handler jmp EXT_INT0 ; IRQ0 Handler jmp EXT_INT1 ; IRQ1 Handler :. :. ; jmp SPM_RDY ; Store Program Memory Ready Handler r16,high(RAMEND); Main program start out SPH,r16 ; Set Stack Pointer to top of RAM ldi r16,low(RAMEND) out SPL,r16 sei ; Enable interrupts <instr> xxx ATmega64A 63 ...
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... Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret /* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to boot Flash section */ MCUCR = (1<<IVSEL); ATmega64A SM0 SM2 IVSEL IVCE R/W R/W R/W R ...
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... If the level is sampled twice by the Watchdog Oscillator clock but ISC31 ISC30 ISC21 ISC20 R/W R/W R/W R Table 12-1 on page will generate an interrupt. Shorter pulses are not guaranteed to generate an inter- ATmega64A 37. Low level interrupts and the 327. The MCU will “Clock Systems and ISC11 ISC10 ISC01 ISC00 R/W R/W R/W R ...
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... The rising edge between two samples of INTn generates an interrupt request When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. ATmega64A Condition Min Typ ...
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... INT7 INT6 INT5 INT4 R/W R/W R/W R INTF7 INTF6 INTF5 INTF4 R/W R/W R/W R for more information. ATmega64A INT3 INT2 INT1 INT0 R/W R/W R/W R INTF3 INTF2 INTF1 INTF0 R/W R/W R/W R “Digital Input ...
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... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description” on page 73. Refer to the individual module sections for a full description of the alternate ATmega64A Figure 13-1. Refer to “Electrical Char Logic See Figure "General Digital I/O" for Details 88. “ ...
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... SLEEP CONTROL clk : I/O CLOCK I/O 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk and PUD are common to all ports. 88, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega64A Figure 13 DDxn Q CLR RESET ...
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... Input 1 1 Input 0 X Output 1 X Output Figure 13-2, the PINxn Register bit and the preceding latch con- pd,max ATmega64A Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 13-3 shows a timing dia- and t respectively ...
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... The out instruction sets the “SYNC LATCH” signal at the positive edge of through the synchronizer is one system clock period. pd SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega64A in r17, PINx XXX 0x00 t pd, max t pd, min , a single signal transition on the pin will be delayed ...
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... Figure 13-2, the digital input signal can be clamped to ground at the input of the /2. CC “Alternate Port Functions” on page ATmega64A 73. 72 ...
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... DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL 1. WPx, WDx, RLx, RPx, and RDx are common to all pins within the same port. clk and PUD are common to all ports. All other signals are unique for each pin. ATmega64A Figure 13-2 can be overridden by PUOExn PUOVxn ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. Analog Input/output This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi- directionally. ATmega64A Fig- 74 ...
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... PORTA7 • PUD PORTA6 • PUD SRE WR | ADA WR | ADA SRE A7 • ADA | D7 OUTPUT A6 • ADA | D6 • WR OUTPUT • INPUT D6 INPUT – ATmega64A PA5/AD5 SRE SRE ~(WR | ADA) • PORTA5 • PUD SRE SRE WR | ADA SRE SRE A5 • ADA | D5 OUTPUT • ...
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... OC0 (Output Compare and PWM Output for Timer/Counter0) MISO (SPI Bus Master Input/Slave Output) MOSI (SPI Bus Master Output/Slave Input) SCK (SPI Bus Serial Clock) SS (SPI Slave Select input) 1. OC1C not applicable in ATmega103 compatibility mode. ATmega64A (1) PA1/AD1 SRE ~(WR | ADA) • PORTA1 • PUD ...
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... Table 13-7 shown in MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. 8160C–AVR–07/09 and Table 13-8 relate the alternate functions of Port B to the overriding signals Figure 13-5 on page 73. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the ATmega64A 77 ...
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... SPE • MSTR SPE • MSTR 0 0 SPE • MSTR SPE • MSTR SPI SLAVE OUTPUT SPI MSTR OUTPUT SPI MSTR INPUT SPI SLAVE INPUT – – ATmega64A PB5/OC1A PB4/OC0 OC1A ENABLE OC0 ENABLE OC1A OC0B 0 ...
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... SRE • (XMM< SRE • (XMM<1) SRE • (XMM<2) A11 A10 – – – – ATmega64A PC5/A13 PC4/A12 SRE • (XMM<3) SRE • (XMM< SRE • (XMM<3) SRE • (XMM< SRE • (XMM<3) SRE • (XMM< ...
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... Interrupt2 Input or UART1 Receive Pin) (1) INT1/SDA (External Interrupt1 Input or TWI Serial DAta) (1) INT0/SCL (External Interrupt0 Input or TWI Serial CLock) 1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode. ATmega64A (1) PC1/A9 PC0/A8 SRE • (XMM<7) SRE • (XMM< SRE • (XMM<7) SRE • ...
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... I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup- press spikes shorter than the input signal, and the pin is driven by an open drain driver with slew-rate limitation. Table 13-13 shown in 8160C–AVR–07/09 and Table 13-14 relates the alternate functions of Port D to the overriding signals Figure 13-5 on page 73. ATmega64A 81 ...
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... When enabled, the Two-wire Serial Interface enables Slew-rate controls on the output pins PD0 and PD1. This is not shown on the figure. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. ATmega64A PD5/XCK1 PD4/ICP1 ...
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... Comparator Negative Input or Output Compare and PWM Output A for Timer/Counter3) (1) AIN0/XCK0 (Analog Comparator Positive Input or USART0 external clock input/output) PDO/TXD0 (Programming Data Output or UART0 Transmit Pin) PDI/RXD0 (Programming Data Input or UART0 Receive Pin) 1. ICP3, T3, OC3C, OC3B, OC3B, OC3A, and XCK0 not applicable in ATmega103 compatibility mode. ATmega64A Table 13-15. 83 ...
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... PDO/TXD0 – Port E, Bit 1 PDO, SPI Serial Programming Data output. During Serial Program Downloading, this pin is used as data output line for the ATmega64A. TXD0, UART0 Transmit Pin. • PDI/RXD0 – Port E, Bit 0 PDI, SPI Serial Programming Data input. During serial program downloading, this pin is used as data input line for the ATmega64A ...
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... ADC5/TMS (ADC input channel 5 or JTAG Test mode Select) ADC4/TCK (ADC input channel 4 or JTAG Test Clock) ADC3 (ADC input channel 3) ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel 0) ATmega64A PE1/PDO/TXD0 PE0/PDI/RXD0 TXEN0 RXEN0 0 PORTE0 • PUD ...
Page 86
... PF7/ADC7/TDI PF6/ADC6/TDO JTAGEN JTAGEN 1 0 JTAGEN JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN 0 TDO JTAGEN JTAGEN 0 0 – – TDI/ADC7 INPUT ADC6 INPUT ATmega64A . . PF5/ADC5/TMS PF4/ADC4/TCK JTAGEN JTAGEN 1 1 JTAGEN JTAGEN JTAGEN JTAGEN 0 0 – – TMS/ADC5 INPUT ...
Page 87
... ADC3 INPUT ADC2 INPUT Alternate Function TOSC1 (RTC Oscillator Timer/Counter0) TOSC2 (RTC Oscillator Timer/Counter0) ALE (Address Latch Enable to external memory) RD (Read strobe to external memory) WR (Write strobe to external memory) ATmega64A PF1/ADC1 PF0/ADC0 ...
Page 88
... Port G to the overriding signals Figure 13-5 on page 73. PG4/TOSC1 AS0 0 AS0 AS0 0 – T/C0 OSC INPUT PORTA7 PORTA6 PORTA5 PORTA4 R/W R/W R/W R ATmega64A PG3/TOSC2 PG2/ALE AS0 SRE 0 0 AS0 SRE SRE 0 ALE AS0 – – T/C0 OSC OUTPUT – PG0/WR SRE 0 SRE 1 ...
Page 89
... R/W R/W R/W R DDC7 DDC6 DDC5 DDC4 R/W R/W R/W R PINC7 PINC6 PINC5 PINC4 N/A N/A N/A N/A ATmega64A DDA3 DDA2 DDA1 DDA0 R/W R/W R/W R PINA3 PINA2 PINA1 PINA0 N/A N/A N/A N PORTB3 PORTB2 PORTB1 PORTB0 ...
Page 90
... N/A N/A N/A N PORTF7 PORTF6 PORTF5 PORTF4 R/W R/W R/W R DDF7 DDF6 DDF5 DDF4 R/W R/W R/W R ATmega64A PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R DDD3 DDD2 DDD1 DDD0 R/W R/W R/W R PIND3 PIND2 PIND1 PIND0 ...
Page 91
... PING4 N TSM – – – ACME R R for more details about this feature. ATmega64A PINF3 PINF2 PINF1 PINF0 N/A N/A N/A N PORTG3 PORTG2 PORTG1 PORTG0 R/W R/W R/W R ...
Page 92
... Control Logic direction BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = OCRn Synchronized Status Flags Status Flags ASSRn Asynchronous Mode Select (ASn) ATmega64A Figure 14-1. For the actual placement of TOVn (Int. Req.) clk Tn TOSC1 T/C Oscillator Prescaler TOSC2 clk OCn I/O (Int. Req.) Waveform OCn ...
Page 93
... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The assignment is dependent on the mode of operation default equal to the MCU clock, clk T0 108. For details on clock sources and prescaler, see 105. ATmega64A See “Output . When the AS0 I/O “ASSR Figure 93 ...
Page 94
... present or not. A CPU write overrides (has priority over) all counter clear or T0 97. can be used for generating a CPU interrupt. TOV0 97). Figure 14-3 shows a block diagram of the Output Compare unit. ATmega64A TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler clk TOSC1 TOSC2 I/O (“ ...
Page 95
... The setup of the OC0 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0 value is to use the Force Output Compare 8160C–AVR–07/09 DATA BUS OCRn TCNTn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 COMn1:0 ATmega64A OCFn (Int.Req.) OCxy 95 ...
Page 96
... The design of the Output Compare pin logic allows initialization of the OC0 state before the out- put is enabled. Note that some COM01:0 bit settings are reserved for certain modes of operation. 8160C–AVR–07/09 COMn1 Waveform COMn0 Generator FOCn clk I/O See “Register Description” on page 106. ATmega64A Figure 14-4 shows a simplified sche OCn Pin OCn ...
Page 97
... Compare Match occurs between TCNT0 and OCR0, and then counter (TCNT0) is cleared. 8160C–AVR–07/09 Table 14-3 on page 107. For fast PWM mode, refer to Table 14-5 on page 96.). “Timer/Counter Timing Diagrams” on page Figure ATmega64A Table 14-4 on page 107. 101. 14-5. The counter value (TCNT0) 97 ...
Page 98
... The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in 8160C–AVR–07/ clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 + Figure 14-6. The TCNT0 value is in the timing diagram shown as a his- ATmega64A OCn Interrupt Flag Set (COMn1 OC0 clk_I ...
Page 99
... Compare unit is enabled in the fast PWM mode. 8160C–AVR–07/ Table 14-4 on page f clk_I ----------------- - OCnPWM ⋅ N 256 = f oc0 clk_I/O ATmega64A OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 107). The actual OC0 /2 when OCR0 is set to zero. This fea- 99 ...
Page 100
... OC0 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0 Register at the Com- 8160C–AVR–07/ Table 14-5 on page ATmega64A Figure 14-7. OCn Interrupt Flag Set OCRn Update TOVn Interrupt ...
Page 101
... Timer/Counter operation. The show the same timing data, but with the prescaler enabled. The figures illustrate contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 ATmega64A f clk_I/O = ----------------- - ⋅ N 510 OCn has a transition from high to low even though Figure 14-7 ...
Page 102
... I/O Tn /8) I/O MAX - 1 shows the setting of OCF0 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. ATmega64A /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 /8) clk_I/O OCRn + 2 102 ...
Page 103
... OCR0 or TCNT0. If the write cycle is not finished, and the MCU enters sleep mode before the OCR0UB bit returns to zero, the device will never receive a Compare Match interrupt, and the MCU will not wake up. 8160C–AVR–07/09 caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega64A TOP BOTTOM TOP BOTTOM + 1 103 ...
Page 104
... The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 8160C–AVR–07/09 ) again becomes active, TCNT0 will read as the previous value (before entering I/O ATmega64A 104 ...
Page 105
... AS0 PSR0 CS00 CS01 CS02 TIMER/COUNTER0 CLOCK SOURCE . By setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked OSC /256, and clk /1024. Additionally, clk T0S T0S ATmega64A 10-BIT T/C PRESCALER 0 clk T0 . clk is by default connected to the main T0S T0S /8, clk /32, clk T0S T0S as well as 0 (stop) may be selected ...
Page 106
... PWM, Phase Correct 1 0 CTC 1 1 Fast PWM 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega64A COM00 WGM01 CS02 CS01 R/W ...
Page 107
... A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See 100 for more details. ATmega64A (1) “Fast PWM Mode” on page 98 (1) “Phase Correct PWM Mode” on page ...
Page 108
... TCNT0[7:0] R/W R/W R/W R OCR0[7:0] R/W R/W R/W R – – – – ATmega64A R/W R/W R/W R R/W R/W R/W R AS0 TCN0UB OCR0UB TCR0UB R When AS0 is I/O TCNT0 ...
Page 109
... Alternatively, OCF0 is cleared by writing a logic one to 8160C–AVR–07/ OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R ATmega64A OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R OCF1B TOV1 OCF0 TOV0 R/W R/W R/W R TIMSK ...
Page 110
... The bit will not be cleared by hardware if the TSM bit is set. 8160C–AVR–07/ TSM – – – R ATmega64A ACME PUD PSR0 PSR321 R/W R/W R/W R SFIOR 110 ...
Page 111
... TCNT1 for accessing Timer/Counter1 counter value and so on). The physical I/O Register and bit locations for ATmega64A are listed in the A simplified block diagram of the 16-bit Timer/Counter is shown in I/O Registers, including I/O bits and I/O pins, are shown in bold. ...
Page 112
... Count Clear Control Logic Direction Timer/Counter TCNTx = OCRxA = OCRxB = OCRxC ICRx TCCRxA 1. Refer to Figure 1-1 on page 2, Table 13-6 on page Timer/Counter1 and 3 pin placement and description. ATmega64A (1) TOVx (Int.Req.) Clock Select TCLK Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCFxA (Int.Req.) Waveform Generation OCFxB Fixed (Int ...
Page 113
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCRnA or ICRn Reg- ister. The assignment is dependent of the mode of operation. ATmega64A (See 113 ...
Page 114
... The assembly code example returns the TCNTn value in the r17:r16 register pair. 8160C–AVR–07/09 ( Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH :. (1) unsigned int Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into TCNTn See “About Code Examples” on page 8. ATmega64A 114 ...
Page 115
... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNTn into TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “About Code Examples” on page 8. The assembly code example returns the TCNTn value in the r17:r16 register pair. ATmega64A 115 ...
Page 116
... SREG = sreg; 1. See “About Code Examples” on page 8. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNTn. “Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers” on page shows a block diagram of the counter and its surroundings. ATmega64A 143. 116 ...
Page 117
... Signalize that TCNTn has reached minimum value (zero). ). The clk can be generated from an external or internal clock present or not. A CPU write overrides (has priority over) all counter clear “Modes of Operation” on page ATmega64A TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 123 ...
Page 118
... ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn 1. The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not Timer/Counter3. ATmega64A Figure 15-3. The elements of (1) DATA BUS (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ...
Page 119
... Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn 8160C–AVR–07/09 114. ATmega64A “Accessing 16-bit Registers” (Figure 16-1 on page 143). The edge detector is also ...
Page 120
... TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP Waveform Generator BOTTOM WGMn3:0 ATmega64A 123.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) COMnx1:0 OCnx 120 ...
Page 121
... Normal mode. The OCnx Register keeps its value even when changing between waveform generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. 8160C–AVR–07/09 114. ATmega64A “Accessing 16-bit Registers” 121 ...
Page 122
... Note that some COMnx1:0 bit settings are reserved for certain modes of operation. The COMnx1:0 bits have no effect on the Input Capture unit. 8160C–AVR–07/09 Waveform Generator I/O See “16-bit Timer/Counter Register Description” on page 133. ATmega64A Figure 15-5 shows a simplified OCnx Pin ...
Page 123
... Compare Match output frequency. It also simplifies the oper- ation of counting external events. 8160C–AVR–07/09 Table 15-2 on page 134, and for phase correct and phase and frequency correct PWM refer to 134. “Timer/Counter Timing Diagrams” on page ATmega64A 133. For fast PWM mode refer to 122.) 130. Table 15-3 Table 15-4 123 ...
Page 124
... OCRnA is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ ATmega64A Figure 15-6. The counter value (TCNTn) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA ...
Page 125
... Compare Match will never occur between the TCNTn and the OCRnx. Note 8160C–AVR–07/09 ( TOP log R = ---------------------------------- - FPWM log ATmega64A ) Figure 15-7. The figure OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 126
... The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is 8160C–AVR–07/09 Table 15-3 on page f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCRnA is set to zero (0x0000). This feature clk_I/O ATmega64A 134). The actual ) 126 ...
Page 127
... If the TOP value is lower than any of the com- 8160C–AVR–07/ TOP log + ---------------------------------- - PCPWM log ATmega64A Figure 15-8. The figure OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 127 ...
Page 128
... The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see 8 and Figure 8160C–AVR–07/09 f OCnxPCPWM 15-9). ATmega64A Figure 15-8 illustrates, changing the TOP Table 15-4 on page f clk_I/O = --------------------------- - ⋅ ...
Page 129
... R = ---------------------------------- - PFCPWM Figure 15-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- ATmega64A ( ) TOP log OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and ...
Page 130
... TCNTn OCRnx OCFnx Figure 15-11 8160C–AVR–07/09 f OCnxPFCPWM Figure 15-10 I/O Tn /1) I/O OCRnx - 1 shows the same timing data, but with the prescaler enabled. ATmega64A f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCFnx. OCRnx OCRnx + 1 OCRnx Value ...
Page 131
... I/O clk Tn (clk /1) I/O TCNTn TOP - 1 TCNTn TOP - 1 (FPWM) (if used as TOP) OCRnx Old OCRnx Value shows the same timing data, but with the prescaler enabled. ATmega64A OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 BOTTOM + 1 TOP - 2 131 ...
Page 132
... Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f (CTC and FPWM) (PC and PFC PWM) and ICFn (Update at TOP) 8160C–AVR–07/09 clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 TCNTn TOP - 1 TOVn (FPWM) (if used as TOP) OCRnx Old OCRnx Value ATmega64A /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 New OCRnx Value TOP - 2 132 ...
Page 133
... COMnB0/ COMnC0 Description 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected Toggle OCnA/OCnB/OCnC on Compare Match Clear OCnA/OCnB/OCnC on Compare Match (Set output to low level Set OCnA/OCnB/OCnC on Compare Match (Set output to high level). ATmega64A COM1B0 COM1C1 COM1C0 WGM11 R/W R/W R/W R ...
Page 134
... OCnA/OCnB/OCnC on Compare Match when downcounting special case occurs when OCRnA/OCRnB/OC COMnA1/COMnB1/COMnC1 is set. details. Table 15-5. Modes of operation supported by the Timer/Counter ATmega64A (1) for more details equals TOP and See “Phase Correct PWM Mode” on page 126. (See “Modes of Operation” on page for more 123 ...
Page 135
... ICNC1 ICES1 – WGM13 R/W R ICNC3 ICES3 – WGM33 R/W R ATmega64A Update of TOP OCRn 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCRnA Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICRn BOTTOM OCRnA BOTTOM ICRn TOP OCRnA ...
Page 136
... External clock source on Tn pin. Clock on falling edge External clock source on Tn pin. Clock on rising edge FOC1A FOC1B FOC1C – ATmega64A – – – – Figure TCCR1C 136 ...
Page 137
... FOC3A FOC3B FOC3C – TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R TCNT3[15:8] TCNT3[7:0] R/W R/W R/W R ATmega64A – – – – R/W R/W R/W R R/W R/W R/W R See “Accessing 16-bit ...
Page 138
... OCR3A[15:8] OCR3A[7:0] R/W R/W R/W R OCR3B[15:8] OCR3B[7:0] R/W R/W R/W R OCR3C[15:8] OCR3C[7:0] R/W R/W R/W R See “Accessing 16-bit Registers” on page 114. ATmega64A R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R/W 0 ...
Page 139
... OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. ATmega64A ICR1[15:8] ICR1[7:0] R/W R/W R/W R ...
Page 140
... Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF1C flag, located in ETIFR, is set. 8160C–AVR–07/ – – TICIE3 OCIE3A This register is not available in ATmega103 compatibility mode. ATmega64A ( OCIE3B TOIE3 OCIE3C R/W R/W R/W R ...
Page 141
... This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections – – ICF3 OCF3A R/W R/W R/W R ATmega64A OCF1B TOV1 OCF0 R/W R/W R/W R Table 15-5 on page 135 3 ...
Page 142
... Note that a Forced Output Compare (FOC1C) strobe will not set the OCF1C flag. OCF1C is automatically cleared when the Output Compare Match 1 C Interrupt Vector is exe- cuted. Alternatively, OCF1C can be cleared by writing a logic one to its bit location. 8160C–AVR–07/09 ATmega64A Table 14-2 on page 106 for the TOV3 flag 142 ...
Page 143
... Alternatively, one of four taps from the prescaler can be used as a CLK_I/O /clk ). The Tn pin is sampled once every system clock cycle by the pin synchroniza /clk clk I/O ATmega64A /8, f CLK_I/O CLK_I/O /clk pulse for each positive (CSn2 nega Edge Detector /64, f ...
Page 144
... Since the edge detector uses ExtClk clk_I/O CK PSR321 T2 0 CS30 CS20 CS31 CS21 CS32 CS22 TIMER/COUNTER3 CLOCK SOURCE clk T3 1. The synchronization logic on the input pins (T3/T2/T1) is shown in ATmega64A 10-BIT T/C PRESCALER Clear CS10 CS11 CS12 TIMER/COUNTER2 CLOCK SOURCE TIMER/COUNTER1 CLOCK SOURCE clk T2 Figure /2.5. clk_I/O (1) ...
Page 145
... The bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter3 Timer/Counter2, and Timer/Counter1 share the same prescaler and a reset of this prescaler will affect all three timers. 8160C–AVR–07/ TSM – – – R ATmega64A ACME PUD PSR0 PSR321 R/W R/W R/W R SFIOR 145 ...
Page 146
... Configuration” on page 2. CPU accessible I/O Registers, including I/O bits 157. TCCRn count clear Control Logic direction BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = OCRn ATmega64A Figure 17-1. For the actual placement of TOVn (Int.Req.) Clock Select clk Tn Edge Tn Detector ( From Prescaler ) OCn (Int.Req.) Waveform OCn Generation ...
Page 147
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The assignment is dependent on the mode of operation. “Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers” on page ATmega64A ). T2 143. Figure ...
Page 148
... Signalize that TCNT2 has reached maximum value. Signalize that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 151. ATmega64A TOVn (Int.Req.) Clock Select Edge Detector clk Tn ( From Prescaler ) top in the following ...
Page 149
... Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the Compare Match will be missed, resulting in incorrect wave- 8160C–AVR–07/09 DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 COMn1:0 ATmega64A TCNTn OCFn (Int.Req.) OCn 149 ...
Page 150
... Generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Regis- 8160C–AVR–07/09 COMn1 Waveform COMn0 Generator FOCn clk I/O ATmega64A Figure 17-4 shows a simplified sche OCn OCn 0 D ...
Page 151
... This mode allows greater control of the Compare Match output frequency. It also sim- plifies the operation of counting external events. 8160C–AVR–07/09 See “Register Description” on page 157. Table 17-3 on page 158. For fast PWM mode, refer to Table 17-5 on page Figure ATmega64A Table 17-4 on page 159. 17-8, Figure 17-9, Figure 17-10, and 155 ...
Page 152
... This high frequency makes the fast PWM mode well suited 8160C–AVR–07/09 Figure clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 + ATmega64A 17-5. The counter value (TCNT2) OCn Interrupt Flag Set (COMn1 OC2 clk_I/O ) 152 /2 ...
Page 153
... Figure 17-6. The TCNT2 value is in the timing diagram shown as a his Table 17-4 on page f clk_I ----------------- - OCnPWM ⋅ N 256 ATmega64A OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 159). The actual OC2 153 ...
Page 154
... TCNT2 slopes represent Compare Matches between OCR2 and TCNT2. Figure 17-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period 8160C–AVR–07/ when OCR2 is set to zero. This fea- OC2 clk_I ATmega64A Figure 17-7. OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 154 ...
Page 155
... MAX value in all modes other than phase correct PWM mode. 8160C–AVR–07/09 f OCnPCPWM Figure 17-7 OCn has a transition from high to low even though Figure Figure 17-8 contains timing data for basic Timer/Counter operation. The figure ATmega64A Table 17-5 on page f clk_I/O = ----------------- - ⋅ N 510 17-7. When the OCR2 value is MAX the ) is therefore shown 159) ...
Page 156
... I/O clk Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. clk I/O clk Tn /8) I/O MAX - 1 TOVn shows the setting of OCF2 in all modes except CTC mode. ATmega64A MAX BOTTOM BOTTOM + 1 /8) clk_I/O MAX BOTTOM BOTTOM + 1 156 ...
Page 157
... Tn /8) I/O OCRn - 1 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. caler (f /8) clk_I/O I/O Tn /8) I/O TOP - FOC2 WGM20 COM21 W R/W R ATmega64A OCRn OCRn + 1 OCRn Value TOP BOTTOM TOP COM20 WGM21 CS22 CS21 R/W R/W R/W R /8) clk_I/O ...
Page 158
... Compare Output Mode, non-PWM Mode COM20 Description 0 0 Normal port operation, OC2 disconnected Toggle OC2 on Compare Match Clear OC2 on Compare Match Set OC2 on Compare Match. ATmega64A Table 17-2 and “Modes of Operation” (1) Update of TOV2 Flag TOP OCR2 Set on 0xFF Immediate MAX 0xFF TOP ...
Page 159
... I clk /1024 (From prescaler) I External clock source on T2 pin. Clock on falling edge External clock source on T2 pin. Clock on rising edge. ATmega64A (1) “Fast PWM Mode” on page 152 (1) “Phase Correct PWM Mode” on page 159 ...
Page 160
... OCR2[7:0] R/W R/W R/W R OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R ATmega64A R/W R/W R/W R R/W R/W R/W R OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R OCF1B ...
Page 161
... When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Inter- rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 8160C–AVR–07/09 ATmega64A 161 ...
Page 162
... Timer/Counter units and the Port B pin 7 output driver circuit.Output Com- pare Modulator, Schematic. 8160C–AVR–07/09 “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” and “8-bit Timer/Counter2 with PWM” on page Timer/Counter1 OC1C Timer/Counter2 OC2 (Figure 18-1). ATmega64A 146. Note that this feature is not Pin OC1C/ OC2/PB7 Figure . The schematic 162 ...
Page 163
... Q PORTB7 DATA BUS illustrates the modulator in action. In this example the Timer/Counter1 is set to oper- clk I/O OC1C OC2 (CTC Mode) PB7 (PORTB7 = 0) PB7 (PORTB7 = 1) 1 (Period) ATmega64A Modulator DDRB7 2 3 Figure 18-2 at the second and third period of the Vcc Pin OC1C / ...
Page 164
... Note: The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega64A and peripheral devices or between several AVR devices. The interconnection between Master and Slave CPUs with SPI is shown in Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave ...
Page 165
... Functions” on page 8160C–AVR–07/09 MSB MASTER LSB MISO 8 BIT SHIFT REGISTER MOSI SPI SCK CLOCK GENERATOR Table 19-1. For more details on automatic port overrides, refer to 73. ATmega64A MSB SLAVE LSB MISO 8 BIT SHIFT REGISTER MOSI SHIFT ENABLE SCK SS “Alternate Port 165 ...
Page 166
... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See “Alternate Functions of Port B” on page 76 direction of the user defined SPI pins. ATmega64A Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 166 ...
Page 167
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page 8. ATmega64A 167 ...
Page 168
... SPI_SlaveReceive ; Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. See “About Code Examples” on page 8. ATmega64A 168 ...
Page 169
... Data bits are shifted out and latched in on opposite edges of the SCK sig- and Table 19-4, as done below: CPOL and CPHA Functionality Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) ATmega64A Figure Trailing Edge SPI Mode Setup (Falling) 0 Sample (Falling) 1 Setup (Rising) 2 ...
Page 170
... SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega64A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 2 Bit 3 ...
Page 171
... DORD R/W R/W R Figure 19-3 on page 170 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 19-3 on page 170 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega64A MSTR CPOL CPHA SPR1 R/W R/W R/W R and Figure 19-4 on page 170 Trailing Edge Falling Rising and Figure 19-4 on page 170 ...
Page 172
... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega64A is also used for program memory and EEPROM down- loading or uploading. See 8160C–AVR–07/09 Table 19-5 ...
Page 173
... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8160C–AVR–07/ MSB R/W R/W R/W R ATmega64A LSB R/W R/W R/W R SPDR Undefined 173 ...
Page 174
... Double Speed Asynchronous Communication Mode 20.1.1 Dual USART The ATmega64A has two USART’s, USART0 and USART1. The functionality for both USART’s is described below. USART0 and USART1 have different I/O Registers as shown in Summary” on page neither is the UBRR0H or UCRS0C registers. This means that in ATmega103 compatibility mode, the ATmega64A supports asynchronous operation of USART0 only ...
Page 175
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1-1 on page 2, Table 13-12 on page USART pin placement. ATmega64A Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN TxD ...
Page 176
... Sync Edge Register Detector xcki XCK xcko Pin DDR_XCK UCPOL Transmitter clock (Internal Signal). Receiver base clock (Internal Signal). Input from XCK pin (internal Signal). Used for synchronous slave ATmega64A Figure 20-1) if the buffer registers are U2X / DDR_XCK txclk ...
Page 177
... The baud rate is defined to be the transfer rate in bit per second (bps). Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRnH and UBRRnL Registers 4095) to Table 20-7 on page 195. ATmega64A Figure 20-2. /(UBRRn+1)). The transmitter divides the OSC Equation for Calculating (1) ...
Page 178
... Figure 20-2 for details. depends on the stability of the system clock source therefore recommended to osc UCPOLn = 1 XCK RxD / TxD UCPOLn = 0 XCK RxD / TxD Figure 20-3 shows, when UCPOLn is zero the data will be changed at ATmega64A f OSC < f ---------- - XCK 4 Sample Sample 178 ...
Page 179
... even n 1 – ⊕ odd n 1 – Parity bit using even parity even Parity bit using odd parity odd Data bit n of the character n ATmega64A FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...
Page 180
... UCSRnC,r16 out ret (1) :. USART_Init ( MYUBRR ); :. /* Set baud rate */ UBRRnH = (unsigned char)(ubrr>>8); UBRRnL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRnB = (1<<RXENn)|(1<<TXENn); /* Set frame format: 8data, 2stop bit */ UCSRnC = (1<<USBSn)|(3<<UCSZn0); 1. See “About Code Examples” on page 8. ATmega64A 180 ...
Page 181
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega64A 181 ...
Page 182
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega64A 182 ...
Page 183
... A second stop bit will be ignored by the Receiver. When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location. 8160C–AVR–07/09 ATmega64A 183 ...
Page 184
... UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret (1) /* Wait for data to be received */ while ( !(UCSRnA & (1<<RXCn Get and return received data from buffer */ return UDRn; 1. See “About Code Examples” on page 8. ATmega64A 184 ...
Page 185
... Get status and ninth bit, then data */ /* from buffer */ status = UCSRnA; resh = UCSRnB; resl = UDRn error, return - status & (1<<FEn)|(1<<DORn)|(1<<UPEn) ) return -1; /* Filter the ninth bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page 8. ATmega64A 185 ...
Page 186
... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error n (UPEn) flag can then be read by software to check if the frame had a Parity Error. 8160C–AVR–07/09 “Parity Bit Calculation” on page 179 ATmega64A and “Parity Checker” on page 186. 186 ...
Page 187
... RxD line is idle (i.e., no communication activity). 8160C–AVR–07/09 (1) sbis UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush (1) unsigned char dummy; while ( UCSRnA & (1<<RXCn) ) dummy = UDRn; 1. See “About Code Examples” on page 8. ATmega64A Figure 20-5 187 ...
Page 188
... IDLE Figure 20 ATmega64A START shows the sampling of the data bits and BIT ...
Page 189
... R is the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. and Table 20-3 list the maximum Receiver baud rate error that can be tolerated. Note ATmega64A STOP 1 (A) ( ...
Page 190
... Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = (%) R (%) slow fast 5 94.12 105.66 6 94.92 104.92 7 95.52 104.35 8 96.00 103.90 9 96.39 103.53 10 96.70 103.23 ATmega64A Max Total Error Recommended Max Receiver (%) Error (%) +6.67/-6.8 ±3.0 +5.79/-5.88 ±2.5 +5.11/-5.19 ±2.0 +4.58/-4.54 ±2.0 +4.14/-4.19 ±1.5 +3.78/-3.83 ±1.5 Max Total Error Recommended Max Receiver (%) Error (%) +5.66/-5.88 ±2.5 +4.92/-5.08 ±2.0 +4.35/-4.48 ±1.5 +3.90/-4.00 ± ...
Page 191
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCMn bit shares the same I/O location as the TXCn flag and this might accidentally be cleared when using SBI or CBI instructions. 8160C–AVR–07/09 ATmega64A 191 ...
Page 192
... ATmega64A Table 20-4 on page 192 189). The error values are calculated ⎞ Closest Match • – 100% ⎠ BaudRate f = 2.0000 MHz osc U2X = 1 U2X = 0 UBRRn Error UBRRn Error 95 0 ...
Page 193
... U2X = 1 U2X = 0 Error UBRRn Error UBRRn 0.0% 103 0.2% 0.0% 51 0.2% 0.0% 25 0.2% 0.0% 16 2.1% 0.0% 12 0.2% 0.0% 8 -3.5% 0.0% 6 -7.0% 0.0% 3 8.5% 0.0% 2 8.5% 0.0% 1 8.5% 0.0% 0 8.5% -7.8% 0 0.0% -7.8% – – – – – 250 kbps ATmega64A f = 7.3728 MHz osc U2X = 1 U2X = 0 Error UBRRn Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0.8% 31 0.0% 25 0.2% 23 0.0% 16 2.1% 15 0.0% 12 0.2% 11 0.0% 8 -3.5% 7 0.0% 6 -7.0% 5 0.0% 3 8.5% 3 0. ...
Page 194
... U2X = 0 Error UBRRn Error UBRRn -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% 0.2% 17 0.0% 2.1% 11 0.0% 0.2% 8 0.0% -3.5% 5 0.0% 8.5% 2 0.0% 0.0% 2 -7.8% 0.0% – – 0.0% – – 1 Mbps 691.2 kbps ATmega64A MHz f = 14.7456 MHz osc U2X = 1 U2X = 0 Error UBRRn Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0.0% 95 0.0% 63 0.0% 71 0.0% 47 0.0% 47 0.0% 31 0.0% 35 0.0% 23 0.0% 23 0.0% 15 0.0% 17 0.0% 11 0.0% 11 0.0% 7 ...
Page 195
... Error UBRRn Error UBRRn 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% 0.2% 29 0.0% -0.8% 19 0.0% 0.2% 14 0.0% 2.1% 9 0.0% -3.5% 4 0.0% 0.0% 4 -7.8% 0.0% – – 0.0% – – 2 Mbps 1.152 Mbps ATmega64A f = 20.0000 MHz osc U2X = 1 U2X = 0 Error UBRRn Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0.0% 86 -0.2% 119 0.0% 64 0.2% 79 0.0% 42 0.9% 59 0.0% 32 -1.4% 39 0.0% 21 -1.4% 29 0.0% 15 1.7% 19 0.0% 10 -1. ...
Page 196
... UDREn is set after a reset to indicate that the Transmitter is ready. 8160C–AVR–07/ RXB[7:0] TXB[7:0] R/W R/W R/W R RXCn TXCn UDREn FEn R R ATmega64A R/W R/W R/W R DORn UPEn U2Xn MPCMn R R R/W R UDnR (Read) UDnR (Write) UCSRnA ...
Page 197
... UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. 8160C–AVR–07/09 “Multi-processor Communication Mode” on page RXCIEn TXCIEn UDRIEn RXENn R/W R/W R/W R ATmega64A 190 TXENn UCSZn2 RXB8n TXB8n UCSRnB R/W R 197 ...
Page 198
... The 8160C–AVR–07/09 ( – UMSELn UPMn1 UPMn0 R/W R/W R/W R This register is not available in ATmega103 compatibility mode. UMSEL Bit Settings UMSELn Mode 0 Asynchronous Operation 1 Synchronous Operation ATmega64A USBSn UCSZn1 UCSZn0 UCPOLn R/W R/W R/W R UCSRnC 198 ...
Page 199
... Transmitted Data Changed (Output of TxD Pin) Rising XCK Edge Falling XCK Edge ATmega64A Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity Stop Bit(s) 1-bit 2-bit UCSZn0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit ...
Page 200
... Writing UBRRnL will trigger an immediate update of the baud rate prescaler. 8160C–AVR–07/09 ( – – – R/W R/W R UBRRH is not available in mega103 compatibility mode ATmega64A – UBRRn[11:8] UBRRn[7: R/W R/W R/W R/W R/W R/W R ...