ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 139

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.11.15 ICR1H and ICR1L – Input Capture Register 1
15.11.16 ICR3H and ICR3L – Input Capture Register 3
15.11.17 TIMSK – Timer/Counter Interrupt Mask Register
8160C–AVR–07/09
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers.
Note:
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 60) is executed when the ICF1 flag, located in TIFR, is set.
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF1A flag, located in TIFR,
is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF1B flag, located in TIFR,
is set.
Bit
0x27 (0x47)
0x26 (0x46)
Read/Write
Initial Value
Bit
(0x81)
(0x80)
Read/Write
Initial Value
Bit
0x37 (0x57)
Read/Write
Initial Value
1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
See “Accessing 16-bit Registers” on page 114.
described in this section. The remaining bits are described in their respective timer sections.
OCIE2
R/W
R/W
R/W
7
0
7
0
7
0
TOIE2
R/W
R/W
R/W
6
0
6
0
6
0
TICIE1
R/W
R/W
R/W
5
0
5
0
5
0
(1)
OCIE1A
R/W
R/W
R/W
4
0
4
0
4
0
ICR3[15:8]
ICR1[15:8]
ICR1[7:0]
ICR3[7:0]
OCIE1B
R/W
R/W
R/W
3
0
3
0
3
0
TOIE1
R/W
R/W
R/W
2
0
2
0
2
0
OCIE0
R/W
R/W
R/W
1
0
1
0
1
0
ATmega64A
TOIE0
R/W
R/W
R/W
0
0
0
0
0
0
ICR3H
ICR1H
ICR3L
TIMSK
ICR1L
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