ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 26

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8160C–AVR–07/09
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guaranteed (varies between devices, temperature, and supply voltage). Conse-
quently the XMEM interface is not suited for synchronous operation.
Figure 7-6.
Note:
Figure 7-7.
Note:
System Clock (CLK
System Clock (CLK
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
SRW00 (lower sector).
The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal
or external).
SRW00 (lower sector).
The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal
or external).
External Data Memory Cycles without Wait State
(SRWn1 = 0 and SRWn0 =0)
External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1
DA7:0
A15:8
CPU
ALE
DA7:0
WR
A15:8
RD
CPU
ALE
WR
)
RD
)
Prev. Addr.
Prev. Data
Prev. Data
Prev. Data
Prev. addr.
Prev. data
Prev. data
Prev. data
T1
T1
Address
Address
Address
T2
Address
Address
Address
XX
T2
XX
XXXXX
Address
T3
Data
Data
Data
Address
T3
Data
Data
Data
(1)
T4
ATmega64A
XXXXXXXX
T4
T5
(1)
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