ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 30

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.6
7.6.1
7.6.2
8160C–AVR–07/09
Register Description
MCUCR – MCU Control Register
XMCRA – External Memory Control Register A
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,
ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin
direction settings in the respective data direction registers. Writing SRE to zero, disables the
External Memory Interface and the normal pin and data direction settings are used.
• Bit 6 – SRW10: Wait State Select Bit
For a detailed description in non ATmega103 compatibility mode, see common description for
the SRWn bits below (XMRA description). In ATmega103 compatibility mode, writing SRW10 to
one enables the wait state and one extra cycle is added during read/write strobe as shown in
Figure
• Bit 7 – Res: Reserved Bit
This is a reserved bit and will always read as zero. When writing to this address location, write
this bit to zero for compatibility with future devices.
• Bit 6:4 – SRL2, SRL1, SRL0: Wait State Sector Limit
It is possible to configure different wait states for different external memory addresses. The
external memory address space can be divided in two sectors that have separate wait-state bits.
The SRL2, SRL1, and SRL0 bits select the split of the sectors, see
default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address
space is treated as one sector. When the entire SRAM address space is configured as one sec-
tor, the wait states are configured by the SRW11 and SRW10 bits.
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
(0x6D)
Read/Write
Initial Value
7-7.
SRE
R/W
R
7
0
7
–
0
SRW10
SRL2
R/W
R/W
6
0
6
0
SRL1
R/W
R/W
SE
5
0
5
0
SRL0
SM1
R/W
R/W
4
0
4
0
SRW01
SM0
R/W
R/W
3
0
3
0
SRW00
SM2
R/W
R/W
2
0
2
0
Table 7-2
SRW11
IVSEL
R/W
R/W
1
0
1
0
ATmega64A
and
IVCE
R/W
R
0
0
0
–
0
Figure
MCUCR
XMCRA
7-4. By
30