ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 44

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.10
8.10.1
8.10.2
8160C–AVR–07/09
Register Descriprion
XDIV – XTAL Divide Control Register
OSCCAL – Oscillator Calibration Register
The XTAL Divide Control Register is used to divide the source clock frequency by a number in
the range 2 - 129. This feature can be used to decrease power consumption when the require-
ment for processing power is low.
• Bit 7 – XDIVEN: XTAL Divide Enable
When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals (clk
clk
can be written run-time to vary the clock frequency as suitable to the application.
• Bits 6:0 – XDIV6:XDIV0: XTAL Divide Select Bits 6 - 0
These bits define the division factor that applies when the XDIVEN bit is set (one). If the value of
these bits is denoted d, the following formula defines the resulting CPU and peripherals clock
frequency f
The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is written to
one, the value written simultaneously into XDIV6:XDIV0 is taken as the division factor. When
XDIVEN is written to zero, the value written simultaneously into XDIV6:XDIV0 is rejected. As the
divider divides the master clock input to the MCU, the speed of all peripherals is reduced when a
division factor is used.
Note:
Note:
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
Writing the calibration byte to this address will trim the internal Oscillator to remove process vari-
ations from the Oscillator frequency. During Reset, the 1 MHz calibration value which is located
in the signature row high byte (address 0x00) is automatically loaded into the OSCCAL Register.
If the internal RC is used at other frequencies, the calibration values must be loaded manually.
This can be done by first reading the signature row by a programmer, and then store the calibra-
tion values in the Flash or EEPROM. Then the value can be read by software and loaded into
the OSCCAL Register. When OSCCAL is zero, the lowest available frequency is chosen. Writing
non-zero values to this register will increase the frequency of the internal Oscillator. Writing
Bit
0x3C (0x5C)
Read/Write
Initial Value
Bit
(0x6F)
Read/Write
Initial Value
ADC
, clk
When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock only. The
frequency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down
Source clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter0 registers may
fail.
1. The OSCCAL Register is not available in ATmega103 compatibility mode.
CPU
clk
:
, clk
XDIVEN
CAL7
R/W
R/W
7
7
0
FLASH
) is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit
CAL6
XDIV6
R/W
R/W
6
6
0
(1)
CAL5
XDIV5
R/W
R/W
5
5
0
Device Specific Calibration Value
f
CLK
CAL4
XDIV4
R/W
=
R/W
4
4
0
Source clock
--------------------------------- -
129 d
CAL3
XDIV3
R/W
R/W
–
3
3
0
CAL2
XDIV2
R/W
R/W
2
2
0
XDIV1
CAL1
R/W
R/W
1
1
0
ATmega64A
XDIV0
CAL0
R/W
R/W
0
0
0
OSCCAL
XDIV
I/O
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