ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 91

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.4.18
13.4.19
13.4.20
13.4.21
13.4.22
8160C–AVR–07/09
PINF – Port F Input Pins Address
PORTG – Port G Data Register
DDRG – Port G Data Direction Register
PING – Port G Input Pins Address
SFIOR – Special Function IO Register
Note that PORTF and DDRF Registers are not available in ATmega103 compatibility mode
where Port F serves as digital input only.
Note that PORTG, DDRG, and PING are not available in ATmega103 compatibility mode. In the
ATmega103 compatibility mode Port G serves its alternate functions only (TOSC1, TOSC2, WR,
RD and ALE).
• Bit 2 – PUD: Pull-up disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
figuring the Pin” on page 69
Bit
0x00 (0x20)
Read/Write
Initial Value
Bit
(0x65)
Read/Write
Initial Value
Bit
(0x64)
Read/Write
Initial Value
Bit
(0x63)
Read/Write
Initial Value
Bit
0x20 (0x40)
Read/Write
Initial Value
PINF7
N/A
TSM
R/W
R
R
R
R
7
7
–
0
7
–
0
7
–
0
7
0
PINF6
R
6
–
0
N/A
R
R
R
R
6
0
0
0
6
–
6
–
6
–
for more details about this feature.
R
5
–
0
PINF5
N/A
R
R
R
R
5
5
–
0
5
–
0
5
–
0
R
4
–
0
PORTG4
PING4
PINF4
DDG4
R/W
R/W
N/A
N/A
R
R
4
4
0
4
0
4
ACME
R/W
3
0
PORTG3
PING3
PINF3
DDG3
R/W
R/W
N/A
N/A
R
3
0
R
3
3
0
3
PUD
R/W
2
0
PORTG2
PING2
PINF2
DDG2
R/W
R/W
N/A
N/A
R
R
2
2
0
2
0
2
PSR0
R/W
1
0
PORTG1
PING1
PINF1
DDG1
R/W
R/W
N/A
N/A
R
R
1
1
0
1
0
1
ATmega64A
PSR321
R/W
0
0
PORTG0
PING0
PINF0
DDG0
R/W
R/W
N/A
N/A
R
R
0
0
0
0
0
0
SFIOR
PORTG
DDRG
PING
PINF
“Con-
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