ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 176

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.3
8160C–AVR–07/09
Clock Generation
However, the receive buffering has two improvements that will affect the compatibility in some
special cases:
The following control bits have changed name, but have same functionality and register location:
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register n C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnB Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCK pin is only active when using synchronous mode.
Figure 20-2
Figure 20-2. Clock Generation Logic, Block Diagram
Signal description:
operation.
• A second buffer register has been added. The two buffer registers operate as a circular FIFO
• The Receiver Shift Register can now act as a third buffer level. This is done by allowing the
• CHR9 is changed to UCSZn2.
• OR is changed to DORn.
buffer. Therefore the UDRn must only be read once for each incoming data! More important
is the fact that the error flags (FEn and DORn) and the ninth data bit (RXB8n) are buffered
with the data in the receive buffer. Therefore the status bits must always be read before the
UDRn Register is read. Otherwise the error status will be lost since the buffer state is lost.
received data to remain in the serial Shift Register (see
full, until a new start bit is detected. The USART is therefore more resistant to Data Over Run
(DORn) error conditions.
txclk
rxclk
xcki
DDR_XCK
XCK
Pin
shows a block diagram of the Clock Generation logic.
xcko
xcki
OSC
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave
Down-Counter
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/ 2
/ 4
Figure
/ 2
20-1) if the buffer registers are
DDR_XCK
ATmega64A
U2X
0
1
0
1
0
1
1
0
UMSEL
txclk
rxclk
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