ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 164

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19. SPI – Serial Peripheral Interface
19.1
19.2
8160C–AVR–07/09
Features
Overview
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Figure 19-1. SPI Block Diagram
Note:
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega64A and peripheral devices or between several AVR devices. The interconnection
between Master and Slave CPUs with SPI is shown in
Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle
when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the
data to be sent in their respective Shift Registers, and the Master generates the required clock
pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
1. Refer to
/2/4/8/16/32/64/128
DIVIDER
Figure 1-1 on page
(1)
2, and
Table 13-6 on page 76
Figure
19-2. The system consists of two
for SPI pin placement.
ATmega64A
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