ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 146

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17. 8-bit Timer/Counter2 with PWM
17.1
17.2
17.2.1
8160C–AVR–07/09
Features
Overview
Registers
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Timer/Counter2 is a general purpose, single-channel, 8-bit Timer/Counter module. A simplified
block diagram of the 8-bit Timer/Counter is shown in
I/O pins, refer to
and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in
the
Figure 17-1. 8-bit Timer/Counter Block Diagram
The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt
request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag
Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register
Single Channel Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse width Modulator (PWM)
Frequency Generator
External Event Counter
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)
“Register Description” on page
Timer/Counter
“Pin Configuration” on page
TCNTn
OCRn
=
direction
count
clear
BOTTOM
= 0
157.
Control Logic
=
TCCRn
TOP
0xFF
2. CPU accessible I/O Registers, including I/O bits
Figure
clk
Tn
Generation
Waveform
17-1. For the actual placement of
Clock Select
( From Prescaler )
Detector
Edge
ATmega64A
OCn
(Int.Req.)
TOVn
(Int.Req.)
OCn
Tn
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