ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 337

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 28-7.
Notes:
28.9
Table 28-8.
Notes:
8160C–AVR–07/09
0
1
2
3a
3b
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
R
R
V
REF
AIN
INT
Symbol
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LHLL
AVLL
LLAX_ST
LLAX_LD
AVLLC
AVRL
AVWL
LLWL
LLRL
DVRH
RLDV
RHDX
RLRH
DVWL
WHDX
DVWH
WLWH
1. Minimum for AVCC is 2.7V.
2. Maximum for AVCC is 5.5V.
External Data Memory Timing
1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
CLCL
Parameter
Internal Voltage Reference
Reference Input Resistance
Analog Input Resistance
ADC Characteristics, Differential Channels, -40⋅C – 85⋅C (Continued)
External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state
Parameter
Oscillator Frequency
ALE Pulse Width
Address Valid A to ALE Low
Address Hold After ALE Low,
write access
Address Hold after ALE Low,
read access
Address Valid C to ALE Low
Address Valid to RD Low
Address Valid to WR Low
ALE Low to WR Low
ALE Low to RD Low
Data Setup to RD High
Read Low to Data Valid
Data Hold After RD High
RD Pulse Width
Data Setup to WR Low
Data Hold After WR High
Data Valid to WR High
WR Pulse Width
8 MHz Oscillator
57.5
57.5
47.5
47.5
42.5
Min
115
115
115
115
115
125
115
40
5
5
0
Condition
Max
67.5
67.5
75
0.5t
0.5t
0.5t
0.5t
0.5t
1.0t
1.0t
1.0t
1.0t
1.0t
1.0t
1.0t
CLCL
CLCL
CLCL
CLCL
CLCL
Min
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
0.0
40
Min
5
5
0
2.3
CLCL
Variable Oscillator
-15
-15
-20
-5
-5
-10
-10
-10
-10
-10
-10
(1)
(1)
(2)
(2)
(1)
2.56
Typ
100
32
0.5t
0.5t
ATmega64A
1.0t
CLCL
CLCL
Max
CLCL
16
Max
+5
+5
2.7
-50
(2)
(2)
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
MΩ
kΩ
V
337