SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1146

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

46.11 Touch Screen ADC (TSADC)
Table 46-21. Channel Conversion Time and ADC Clock
Note:
Table 46-22. External Voltage Reference Input
Table 46-23. Analog Inputs
Table 46-24. Transfer Characteristics
1146
Parameter
ADC Clock Frequency
Startup Time
Track and Hold Acquisition Time (TTH)
Conversion Time (TCT)
Throughput Rate
Parameter
ADVREF Input Voltage Range
ADVREF Average Current
Current Consumption on VDDANA
Parameter
Input Voltage Range
Input Leakage Current
Input Capacitance
Input Source Impedance
Parameter
Resolution
Integral Non-linearity
Differential Non-linearity
Offset Error
Gain Error
1. The Track and Hold Acquisition Time is given by:
SAM9G45
The ADC internal clock is divided by 2 in order to generate a clock with a duty cycle of 75%. So the maximum conversion
time is give by:
The full speed is obtained for an input source impedance of < 50 Ohms maximum, or TTH = 500 ns.
In order to make the TSADC work properly, the SHTIM field in TSADCC Mode Register is to be calculated according to this
Track and Hold Acquisition Time, also called Sampled and Hold Time.
TTH (ns)
TCT μs
=
=
500
---------- - MHz
Fclk
23
+
0.12
Z
Conditions
Conditions
10-bit resolution mode
Return from Idle Mode
ADC Clock = 13.2 MHz
ADC Clock = 13.2 MHz
ADC Clock = 13.2 MHz
IN
(1)
(1)
(1)
Min
2.4
Min
0
Min
-0.9
-1.5
Min
0.5
Typ
Typ
50
7
Typ
Typ
0.5
10
VDDANA
ADVREF
6438G–ATARM–19-Apr-11
Max
600
300
Max
Max
13.2
1.75
10
Max
+0.9
440
±10
1
40
±2
±2
Ohms
Units
Units
Units
kSPS
Units
MHz
LSB
LSB
LSB
μA
μA
μA
pF
mV
μs
μs
μs
V
V
bit