SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 227

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22. DDR/SDR SDRAM Controller (DDRSDRC)
22.1
6438G–ATARM–19-Apr-11
Description
The DDR/SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises
four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are inter-
leaved to maximize memory bandwidth and minimize transaction latency due to SDRAM
protocol.The DDRSDRC supports a read or write burst length of 8 locations which frees the
command and address bus to anticipate the next command, thus reducing latency imposed by
the SDRAM protocol and improving the SDRAM bandwidth. Moreover it keeps track of the active
row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in
one bank and data in the other banks. So as to optimize performance, it is advisable to avoid
accessing different rows in the same bank. The DDRSDRC supports a CAS latency of 2 or 3 and
optimizes the read access depending on the frequency.
The features of self refresh, power-down and deep power-down modes minimize the consump-
tion of the SDRAM device.
The DDRSDRC user interface is compliant with ARM Advanced Peripheral Bus (APB rev2).
Note: The term “SDRAM device” regroups SDR-SDRAM, Mobile SDR-SDRAM, Mobile DDR1-
SDRAM and DDR2-SDRAM devices.
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