SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 299

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.5
25.6
25.7
6438G–ATARM–19-Apr-11
Processor Clock Controller
USB Device and Host clocks
LP-DDR/DDR2 Clock
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be disabled by writing the System Clock Disable Register
(PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System
Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock and
entering Wait for Interrupt Mode. The Processor Clock is automatically re-enabled by any
enabled fast or normal interrupt, or by reset of the product.
Note: The ARM Wait for Interrupt mode is entered by means of CP15 coprocessor operation.
Refer to the Atmel application note,
Systems, lit. number 6217.
When the Processor Clock is disabled, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
The USB Device and Host High Speed ports clocks are controlled by the UDPHS and UHPHS
bits in PMC_PCER. To save power on this peripheral when they are is not used, the user can
set these bits in PMC_PCDR. The UDPHS and UHPHS bits PMC_PCSR gives the activity of
these clocks.
The PMC also provides the clocks UHP48M and UHP12M to the USB Host OHCI. The USB
Host OHCI clocks are controlled by the UHP bit in PMC_SCER. To save power on this periph-
eral when it is not used, the user can set the UHP bit in PMC_SCDR. The UHP bit in
PMC_SCSR gives the activity of this clock. The USB host OHCI requires both the 12/48 MHz
signal and the Master Clock. USBDIV field in PMC_USB register is to be programmed to 9 (divi-
sion by 10) for normal operations.
To save more power consumption user can stop UTMI PLL, in this case USB high-speed opera-
tions are not possible. Nevertheless, as the USB OHCI Input clock can be selected with USBS
bit (PLLA or UTMI PLL) in PMC_USB register, OHCI full-speed operation remain possible.
The user must program the USB OHCI Input Clock and the USBDIV divider in PMC_USB regis-
ter to generate a 48 MHz and a 12 MHz signal with an accuracy of ± 0.25%.
The Power Management Controller controls the clocks of the DDR memory. It provides SysClk
DDR internal clock. That clock is used by the DDR Controller to provide DDR control, data and
DDR clock signals.
The DDR clock can be enabled and disabled with DDRCK bit respectively in PMC_SCER and
PMC_SDER registers. At reset DDR clock is disabled to save power consumption.
The Input clock is the same as Master Clock. The Output SysClk DDR Clock is 2xMCK.
In the case MDIV = ‘00’, PCK = MCK and SysClk DDR and DDRCK clocks are not available.
If Input clock is PLLACK/PLLADIV2 the DDR Controller can drive DDR2 and LP-DDR at up to
133MHz with MDIV = ‘11’.
To save PLLA power consumption, the user can choose UPLLCK an Input clock for the system.
In this case the DDR Controller can drive LD-DDR at up to 120MHz.
Optimizing Power Consumption for AT91SAM9261-based
SAM9G45
299