SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 264
SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 264 of 1196
- Download datasheet (20Mb)
22.7.6
Name:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit”.
The Reset Value is 0 Cycle.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 15.
Note: This field is found only in DDR2-SDRAM devices.
• TXARDS: Exit Active Power Down Delay to Read Command in Mode “Slow Exit”.
The Reset Value is 0 Cycle.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 15.
Note: This field is found only in DDR2-SDRAM devices.
• TRPA: Row Precharge All Delay
The Reset Value is 0 Cycle.
This field defines the delay between a Precharge ALL banks Command and another command in number of cycles. Num-
ber of cycles is between 0 and 15.
Note: This field is found only in DDR2-SDRAM devices.
• TRTP: Read to Precharge
The Reset Value is 2 Cycles.
This field defines the delay between Read Command and a Precharge command in number of cycle.
Number of cycles is between 0 and 15.
264
31
23
15
–
–
7
SAM9G45
DDRSDRC Timing 2 Parameter Register
30
22
14
DDRSDRC_T2PR
Read-write
See
–
–
6
TXARDS
Table 22-9
TRTP
29
21
13
5
–
–
28
20
12
4
–
–
“DDRSDRC Write Protect Mode Register” on page
27
19
11
3
–
–
26
18
10
2
–
–
TXARD
TRPA
25
17
9
1
–
–
6438G–ATARM–19-Apr-11
271.
24
16
8
0
–
–
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