SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 799

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

37.4
37.4.1
37.5
37.5.1
6438G–ATARM–19-Apr-11
Product Dependencies
I/O Lines
I/O Lines
Power Management
Access to the USB host operational registers is achieved through the AHB bus slave interface.
The Open HCI host controller and Enhanced HCI host controller initialize master DMA transfers
through the AHB bus master interface as follows:
Memory access errors (abort, misalignment) lead to an “Unrecoverable Error” indicated by the
corresponding flag in the host controller operational registers.
The USB root hub is integrated in the USB host. Several USB downstream ports are available.
The number of downstream ports can be determined by the software driver reading the root
hub’s operational registers. Device connection is automatically detected by the USB host port
logic.
USB physical transceivers are integrated in the product and driven by the root hub’s ports.
Over current protection on ports can be activated by the USB host controller. Atmel’s standard
product does not dedicate pads to external over current protection.
HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The
embedded USB High Speed physical transceivers are controlled by the USB host controller.
HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The
embedded USB High Speed physical transceivers are controlled by the USB host controller.
One transceiver is shared with USB Device (UDP) High Speed. In this case USB Host High
Speed Controller uses only Port A, ie, the signals HFSDPA, HFSDMA, HHSDPA and HHSDMA.
The port B is driven by the UDP High Speed, the output signals are DFSDP, DFSDM, DHSDP
and DHSDM.
The transceiver is automatically selected for Device operation once the UDP High Speed is
enabled.
The USB Host High Speed requires a 48 MHz clock for the embedded High-speed transceivers.
This clock is provided by the UTMI PLL, it is UPLLCK.
In case power consumption is saved by stopping the UTMI PLL, high-speed operations are not
possible. Nevertheless, OHCI Full-speed operations remain possible by selecting PLLACK as
the input clock of OHCI.
The High-speed transceiver returns a 30 MHz clock to the USB Host controller.
The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI full-speed operations.
These clocks must be generated by a PLL with a correct accuracy of ± 0.25% thanks to USBDIV
field.
• Fetches endpoint descriptors and transfer descriptors
• Access to endpoint data from system memory
• Access to the HC communication area
• Write status and retire transfer descriptor
SAM9G45
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