SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 232

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

232
SAM9G45
An additional 200 cycles of clock are required for locking DLL
8. An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. The applica-
9. Program DLL field into the Configuration Register (see
10. A Mode Register set (MRS) cycle is issued to reset DLL. The application must set
11. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks
12. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command
13. Program DLL field into the Configuration Register (see
14. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-
15. Program OCD field into the Configuration Register (see
16. An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. The
17. Program OCD field into the Configuration Register (see
18. An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. The
tion must set Mode to 5 in the Mode Register (see
perform a write access to the DDR2-SDRAM to acknowledge this command. The write
address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For example,
with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the
DDR2-SDRAM write access should be done at the address 0x20400000.
high (Enable DLL reset).
Mode to 3 in the Mode Register (see
access to the DDR2-SDRAM to acknowledge this command. The write address must
be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB DDR2-
SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should
be done at the address 0x20000000.
precharge command into the Mode Register, the application must set Mode to 2 in the
Mode Register (See
SDRAM address to acknowledge this command
(CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register
(see
tion twice to acknowledge these commands.
low (Disable DLL reset).
SDRAM devices, in particular CAS latency, burst length and to disable DLL reset. The
application must set Mode to 3 in the Mode Register (see
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit
128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write
access should be done at the address 0x20000000
high (OCD calibration default).
application must set Mode to 5 in the Mode Register (see
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For exam-
ple, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address,
the DDR2-SDRAM write access should be done at the address 0x20400000.
low (OCD calibration mode exit).
application must set Mode to 5 in the Mode Register (see
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For exam-
ple, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address,
the DDR2-SDRAM write access should be done at the address 0x20400000.
Section 22.7.1 on page
Section 22.7.1 on page
256). Performs a write access to any DDR2-SDRAM loca-
Section 22.7.1 on page
256). Perform a write access to any DDR2-
Section 22.7.1 on page
Section 22.7.3 on page
Section 22.7.3 on page
Section 22.7.3 on page
Section 22.7.3 on page
Section 22.7.1 on page
Section 22.7.1 on page
Section 22.7.1 on page
256) and perform a write
6438G–ATARM–19-Apr-11
256) and
258) to
258) to
258) to
258) to
256)
256)
256)