AD7193 Analog Devices, AD7193 Datasheet - Page 14

• Manufacturer Part Number: AD7193
• Description: 4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7193

• Resolution (bits): 24bit
• # Chan: 4
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni,Usr-Defined Range/Offset
• Ain Range: ± (Vref/Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7193
Pin No.
21
22
23
24
25
27
28
29
30
31
32
Mnemonic
AGND
DGND
AV
DV
SYNC
DOUT/RDY
DIN
MCLK1
MCLK2
SCLK
CS
EPAD
DD
DD
Description
Analog Ground Reference Point.
Digital Ground Reference Point.
Analog Supply Voltage, 3 V to 5.25 V. AV
AV
Digital Supply Voltage, 2.7 V to 5.25 V. DV
with DV
Logic input that allows for synchronization of the digital filters and analog modulators when using a number
of AD7193 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration
control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital
interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to DV
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output
pin to access the output shift register of the ADC. The output shift register can contain data from any of the
on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate
the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next
update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid
data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the
data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the
SCLK rising edge.
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control
registers in the ADC, with the register selection bits of the communications register identifying the
appropriate register.
When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2.
Master Clock Signal for the Device. The AD7193 has an internal 4.92 MHz clock. This internal clock can be
made available on the MCLK2 pin. The clock for the AD7193 can also be provided externally in the form of a
crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin
can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected.
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-
triggered input, making the interface suitable for opto-isolated applications. The serial clock can be
continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous
clock with the information transmitted to or from the ADC in smaller batches of data.
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in
systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT used to interface with the device.
The exposed pad must be connected to AGND.
DD
at 5 V or vice versa.
DD
at 5 V or vice versa.
Rev. C | Page 14 of 56
DD
DD
is independent of DV
is independent of AV
DD
DD
. Therefore, DV
. Therefore, AV
DD
DD
can be operated at 3 V with
can be operated at 3 V
Data Sheet
DD
.