AD7193 Analog Devices, AD7193 Datasheet - Page 40

• Manufacturer Part Number: AD7193
• Description: 4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7193

• Resolution (bits): 24bit
• # Chan: 4
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni,Usr-Defined Range/Offset
• Ain Range: ± (Vref/Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7193
The offset error is, typically, ±150 µV/gain. If the gain is changed,
it is advisable to perform a calibration. A zero-scale calibration
(an internal zero-scale calibration or a system zero-scale calibration)
reduces the offset error to the order of the noise.
The gain error of the AD7193 is factory calibrated at a gain of 1
with a 5 V power supply at ambient temperature. Following this
calibration, the gain error is, typically, ±0.001% at 5 V. Table 27
shows the typical uncalibrated gain error for the different gain
settings.
Table 27. Typical Precalibration Gain Error vs. Gain
Gain
8
16
32
64
128
Precalibration Gain Error (%)
−0.11
−0.20
−0.23
−0.29
−0.39
Rev. C | Page 40 of 56
An internal full-scale calibration reduces the gain error to
±0.001%, typically, when the gain is equal to 1. For higher gains,
the gain error postinternal full-scale calibration is ±0.003%,
typically, when AV
AV
calibration is ±0.005%, typically.
When AV
when performing internal full-scale calibrations. This increases
the calibration time by a factor of 2. The accuracy of the internal
full-scale calibration is further increased if chop is enabled and
a low output data rate is used while performing the calibration.
A system full-scale calibration reduces the gain error to the
order of the noise irrespective of the analog power supply
voltage.
The AD7193 gives the user access to the on-chip calibration
registers, allowing the microprocessor to read the calibration
coefficients of the device and also to write its own calibration
coefficients from prestored values in the EEPROM. A read of
the registers can be performed at any time. However, the ADC
must be placed in power-down or idle mode when writing to
the registers. The values in the calibration registers are 24 bits
wide. The span and offset of the part can also be manipulated
using the registers.
DD
is less than 4.75 V, the gain error after internal full-scale
DD
is less than 4.75 V, the CLK_DIV bit must be set
DD
is equal to or higher than 4.75 V. When
Data Sheet