AD7193 Analog Devices, AD7193 Datasheet - Page 46

• Manufacturer Part Number: AD7193
• Description: 4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7193

• Resolution (bits): 24bit
• # Chan: 4
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni,Usr-Defined Range/Offset
• Ain Range: ± (Vref/Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7193
When a channel change occurs, the modulator and filter reset.
The complete settling time is required to generate the first
conversion after the channel change. Subsequent conversions on
this channel occur at 1/f
When conversions are performed on a single channel and a
step change occurs, the ADC does not detect the change in
analog input; therefore, it continues to output conversions
at the programmed output data rate. However, it is at least two
conversions later before the output data accurately reflects
the analog input. If the step change occurs while the ADC is
processing a conversion, the ADC takes three conversions after
the step change to generate a fully settled result.
The cutoff frequency f
50 Hz/60 Hz Rejection (Sinc
When FS[9:0] is set to 96 and chopping is enabled, the output
data rate is equal to 12.5 Hz for a 4.92 MHz master clock. The
filter response shown in Figure 47 is obtained. The chopping
introduces notches at odd integer multiples of f
due to the sinc filter in addition to the notches introduced by
the chopping mean that simultaneous 50 Hz and 60 Hz rejection
is achieved for an output data rate of 12.5 Hz. The rejection at
50 Hz/60 Hz ± 1 Hz is typically 63 dB, assuming a stable
master clock.
Figure 46. Asynchronous Step Change in Analog Input (Sinc
CONVERSIONS
f
3dB
CHANNEL
ANALOG
OUTPUT
= 0.24 × f
INPUT
ADC
Figure 45. Channel Change (Sinc
CH A
CHANNEL A
ADC
CH A CH A
3dB
1/
ADC
f
ADC
is equal to
.
4
Chop Enabled)
1/
CH B
f
4
CHANNEL B
ADC
Chop Enabled)
SETTLED
FULLY
CH B
ADC
CH B
/2. The notches
4
Chop Enabled)
CH B
CH B
Rev. C | Page 46 of 56
The 50 Hz/60 Hz rejection can be improved by setting the
REJ60 bit in the mode register to 1. With FS[9:0] set to 96
and REJ60 set to 1, the filter response shown in Figure 48
is achieved. The output data rate is unchanged but the 50 Hz/
60 Hz (±1 Hz) rejection is increased to 83 dB typically.
Figure 48. Sinc
–100
–120
–100
–110
–120
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
Figure 47. Sinc
0
0
0
0
4
Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1)
25
25
4
Filter Response (FS[9:0] = 96, Chop Enabled)
50
50
FREQUENCY (Hz)
FREQUENCY (Hz)
75
75
100
100
Data Sheet
125
125
150
150