LPC1850FET256 NXP Semiconductors, LPC1850FET256 Datasheet - Page 112

• Manufacturer Part Number: LPC1850FET256
• Description: The LPC1850FET256 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 17.
C
2.7 V
LPC1850_30_20_10
Preliminary data sheet
Symbol
Read cycle parameters
t
t
t
t
t
t
t
t
t
t
t
Write cycle parameters
t
t
t
t
t
t
t
t
t
t
CSLAV
CSLOEL
CSLBLSL
OELOEH
am
h(D)
CSHBLSH
CSHOEH
OEHANV
CSHEOR
CSLSOR
CSLAV
CSLDV
CSLWEL
CSLBLSL
WELWEH
WEHDNV
WEHEOW
CSLBLSL
BLSLBLSH
BLSHEOW
L
= 22 pF for EMC_Dn C

V
DD(IO)
Dynamic characteristics: Static external memory interface
Parameter
CS LOW to address valid
time
CS LOW to OE LOW time
CS LOW to BLS LOW time
OE LOW to OE HIGH time
memory access time
data input hold time
CS HIGH to BLS HIGH time PB = 1
CS HIGH to OE HIGH time
OE HIGH to address invalid PB = 1
CS HIGH to end of read
time
CS LOW to start of read
time
CS LOW to address valid
time
CS LOW to data valid time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to WE HIGH time
WE HIGH to data invalid
time
WE HIGH to end of write
time
CS LOW to BLS LOW
BLS LOW to BLS HIGH time PB = 0
BLS HIGH to end of write
time

11.9 External memory interface
3.6 V; values guaranteed by design.
[1]
L
= 20 pF for all others; T
Conditions
PB = 1
PB = 1
PB = 1
PB = 1
PB = 1
PB = 1
PB = 0
PB = 0
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 15 December 2011
amb
=

[2]
[3]
[4]
[2]
40
[2]
[2]
[2]
[2]
[5]
[2]
[5]

Min
3.1
0.6 + T
WAITOEN
0.7
0.6 +
(WAITRD 
WAITOEN + 1) 
T
16
0.4
0.4
2.0
2.0
0
3.1
3.1
1.5
0.7
0.6 +
(WAITWR 
WAITWEN + 1) 
T
0.9 + T
0.4 + T
0.7
0.9 +
(WAITWR 
WAITWEN + 1) 
T
1.9 + T
-
C to 85
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)

C; 2.2 V

32-bit ARM Cortex-M3 microcontroller

Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
LPC1850/30/20/10
DD(REG)(3V3)

3.6 V;
Max
1.6
1.3 + T
WAITOEN
1.8
0.4 +
(WAITRD 
WAITOEN + 1) 
T
16 +
(WAITRD 
WAITOEN +1) 
T
-
1.9
1.4
2.6
0
1.8
1.6
1.5
0.2
1.8
0.4 +
(WAITWR 
WAITWEN + 1) 
T
2.3 + T
0.3 + T
1.8
0.1 +
(WAITWR 
WAITWEN + 1) 
T
0.5 + T
cy(clk)
cy(clk)
cy(clk)
cy(clk)
© NXP B.V. 2011. All rights reserved.
cy(clk)
cy(clk)
cy(clk)
cy(clk)

112 of 157
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns