LPC1850FET256 NXP Semiconductors, LPC1850FET256 Datasheet - Page 85

• Manufacturer Part Number: LPC1850FET256
• Description: The LPC1850FET256 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1850_30_20_10
Preliminary data sheet
7.15.5.1 Features
7.16.1.1 Features
7.15.5 Windowed WatchDog Timer (WWDT)
7.16.1 Analog-to-Digital Converter
7.16 Analog peripherals
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
Remark: The LPC1850/30/20/10 contain two 10-bit ADCs.
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32-bit compare value.
32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
Internally resets chip if not periodically reloaded during the programmable time-out
period.
Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (T
multiples of T
The Watchdog Clock (WDCLK) uses the IRC as the clock source.
10-bit successive approximation analog to digital converter.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 to VDDA.
Sampling frequency up to 400 kSamples/s.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer
outputs 8 or 15, or the PWM output MCOA2.
Individual result registers for each A/D channel to reduce interrupt overhead.
DMA support.
All information provided in this document is subject to legal disclaimers.
cy(WDCLK)
Rev. 3.1 — 15 December 2011
 4.
cy(WDCLK)
 256  4) to (T
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
cy(WDCLK)
 2
© NXP B.V. 2011. All rights reserved.
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