LPC1850FET256 NXP Semiconductors, LPC1850FET256 Datasheet - Page 75

• Manufacturer Part Number: LPC1850FET256
• Description: The LPC1850FET256 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1850_30_20_10
Preliminary data sheet
7.13.1.1 Features
7.13.1 State Configurable Timer (SCT) subsystem
7.13.2 General Purpose DMA (GPDMA)
7.13 AHB peripherals
The SCT allows a wide variety of timing, counting, output modulation, and input capture
operations. The inputs and outputs of the SCT are shared with the capture and match
inputs/outputs of the 32-bit general purpose counter/timers.
The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the
two-counter case, in addition to the counter value the following operational elements are
independent for each half:
In the two-counter case, the following operational elements are global to the SCT, but the
last three can use match conditions from either counter:
The DMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
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Two GPIO group interrupts can be triggered by any pin or pins in each port.
State variable
Limit, halt, stop, and start conditions
Values of Match/Capture registers, plus reload or capture control values
Clock selection
Inputs
Events
Outputs
Interrupts
Two 16-bit counters or one 32-bit counter.
Counter(s) clocked by bus clock or selected input.
Up counter(s) or up-down counter(s).
State variable allows sequencing across multiple counter cycles.
Event combines input or output condition and/or counter match in a specified state.
Events control outputs and interrupts.
Selected event(s) can limit, halt, start, or stop a counter.
Supports:
– up to 8 inputs (one input connected internally)
– up to 16 outputs
– 16 match/capture registers
– 16 events
– 32 states
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 15 December 2011
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
© NXP B.V. 2011. All rights reserved.
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