LPC1850FET256 NXP Semiconductors, LPC1850FET256 Datasheet - Page 128

The LPC1850FET256 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2

LPC1850FET256

Manufacturer Part Number
LPC1850FET256
Description
The LPC1850FET256 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
LPC1850_30_20_10
Preliminary data sheet
13.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines
13.4 Standard I/O pin configuration
Connect the crystal on the PCB as close as possible to the oscillator input and output pins
of the chip. Take care that the load capacitors C
crystal usage have a common ground plane. Also connect the external components to the
ground plain. To keep the noise coupled in via the PCB as small as possible, make loops
and parasitics as small as possible. Choose smaller values of C
increase in the PCB layout.
Figure 39
The default configuration for standard I/O pins is input with pull-up enabled. The weak
MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.
Fig 39. Standard I/O pin configuration with analog input
as digital output
as analog input
as digital input
pin configured
pin configured
pin configured
Digital output driver: Open-drain mode enabled/disabled
Digital input: Pull-up enabled/disabled
Digital input: Pull-down enabled/disabled
Digital input: Repeater mode enabled/disabled
Analog input
driver
shows the possible pin modes for standard I/O pins with analog input function:
All information provided in this document is subject to legal disclaimers.
open-drain enable
repeater mode
Rev. 3.1 — 15 December 2011
output enable
analog input
data output
data input
enable
pull-down enable
pull-up enable
select analog input
x1
32-bit ARM Cortex-M3 microcontroller
, C
LPC1850/30/20/10
x2
, and C
V
V
DD(IO)
DD(IO)
strong
pull-up
strong
pull-down
weak
pull-up
weak
pull-down
x3
x1
in case of third overtone
and C
© NXP B.V. 2011. All rights reserved.
x2
V
DD(IO)
ESD
if parasitics
ESD
V
SS
002aag701
128 of 157
PIN

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