ST7FOXK1 STMicroelectronics, ST7FOXK1 Datasheet - Page 48

• Manufacturer Part Number: ST7FOXK1
• Description: Low cost flash 8bit micro
• Manufacturer: STMicroelectronics

Specifications of ST7FOXK1

• 4 To 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 1K write/erase cycles guaranteed Data retention
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wakeup from Halt, Wait and Slow
• A/d Converter: up to 10 input channels

Supply, reset and clock management
6.5.4
48/226
RC Control Register Low (RCCRL)
Reset value: 011x 0x00 (xxh)
Bit 7 = Reserved, must be kept cleared
Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits
Bit 4 = WDGRF Watchdog Reset flag
This bit indicates that the last reset was generated by the watchdog peripheral. It is set by
hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to
ensure a stable cleared state of the WDGRF flag when CPU starts). The WDGRF and the
LVDRF flags areis used to select the reset source (see
page
Table 10.
Bit 3 = Reserved, must be kept cleared
Bit 2 = LVDRF LVD reset flag
Bits 1:0 = Reserved, must be kept cleared
0
7
These bits, as well as CR[9:2] bits in the RCCRH register must be written immediately
after reset to adjust the RC oscillator frequency. Refer to
oscillator on page
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled
by option byte, the LVDRF bit value is undefined.
The LVDRF flag is not cleared when another RESET type occurs (external or
watchdog), the LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can
not.
48).
CR1
Reset source selection
External RESET pin
CR0
RESET source
34.
Watchdog
LVD
WDGRF
Read/write
0
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 10: Reset source selection on
LVDRF
LVDRF
Section 6.1.1: Internal RC
0
0
1
0
WDGRF
X
0
1
0
0