ST7FOXK1 STMicroelectronics, ST7FOXK1 Datasheet - Page 80

• Manufacturer Part Number: ST7FOXK1
• Description: Low cost flash 8bit micro
• Manufacturer: STMicroelectronics

Specifications of ST7FOXK1

• 4 To 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 1K write/erase cycles guaranteed Data retention
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wakeup from Halt, Wait and Slow
• A/d Converter: up to 10 input channels

On-chip peripherals
10.1.4
10.1.5
80/226
The application program must write in the CR register at regular intervals during normal
operation to prevent an MCU reset. This downcounter is free-running: it counts down even if
the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
Table 33.
1. The timing variation shown in
2. The number of CPU clock cycles applied during the Reset phase (256 or 4096) must be taken into account
Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the CR is not used.
Refer to the option byte description in
Using Halt mode with the WDG (WDGHALT option)
If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
Same behavior in active-halt mode.
Interrupts
None.
CR register.
in addition to these timings.
The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset.
counter code
Watchdog timing
WDG
C0h
Table 33: Watchdog
FFh
Table 33
(1)(2)
timing):
is due to the unknown status of the prescaler when writing to the
Section 13 on page
f
CPU
= 8 MHz
[ms]
min
127
1
ST7FOXF1, ST7FOXK1, ST7FOXK2
211.
[ms]
max
128
2