TMP91xy40FG Toshiba, TMP91xy40FG Datasheet
TMP91xy40FG
Specifications of TMP91xy40FG
Related parts for TMP91xy40FG
TMP91xy40FG Summary of contents
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... TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91CW40FG Semiconductor Company ...
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... Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. Preface ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. • ...
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Divider output (8) General-purpose serial interface: 4 channels • Both UART and synchronous transfer modes are supported. (9) 10-bit AD converter (with sample-and-hold): 4 channels (10) Watchdog timer (11) ...
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DVDD Power supply DVSS pins C0 C1 LCD power LCD driver V1 supply circuit power supply V2 V3 Reset pin RESET System controller Test pins AM1, AM0 EMU1, EMU0 Standby controller NMI High-frequency oscillator High- X1 connecting pins frequency X2 ...
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Pin Assignments and Pin Functions The assignment of input/output pins for the TMP91CW40, their names and functions are follows: 2.1 Pin Assignments Figure 2.1.1 shows the pin assignments of the TMP91CW40FG. 1 P82/TC7OUT P82/TC8OUT DVSS DVCC P62/ 5 ALARM ...
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Pin Names and Functions Table 2.2.1 to Table 2.2.2 list the names and functions of the input and output pins of the TMP91CW40. Table 2.2.1 Pin Names and Functions (1/2) Number Pin Name I/O of Pins P50 to P53 ...
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Table 2.2.2 Pin Names and Functions (2/2) Number Pin Name I/O of Pins P93 1 I/O TXD1 Output P94 1 I/O RXD1 Input P95 1 I/O SCLK1 I/O CTS1 Input PA0 1 I/O TXD2 Output PA1 1 I/O RXD2 Input ...
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Operation This section describes the functions and basic operation of the TMP91CW40. 3.1 CPU The TMP91CW40 contains a high-performance 16-bit CPU (900/L1 CPU). For a detailed description of the CPU, refer to “TLCS-900/L1 CPU” in the preceding chapter. Functions ...
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Figure 3.1.1 TMP91CW40 Reset Timings 91CW40-8 TMP91CW40 2008-09-19 ...
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Memory Map Figure 3.2.1 shows a memory map of the TMP91CW40. 000000H Internal I/O (4 Kbytes) 000100H 001000H Internal RAM (4 Kbytes) 002000H 010000H External memory (Access prohibited) FE0000H Internal ROM (128 Kbytes) FFFF00H Vector table (256 bytes) FFFFFFH ...
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System Clock/Standby Control and Noise Reduction The TMP91CW40 incorporates clock gear, standby control and noise reduction circuits to minimize power consumption and noise. Single-clock mode (X1 and X2 pins only) and dual-clock mode (X1, X2, XT1, and XT2 pins) ...
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System Clock Block Diagram Warm-up (for high- and low-frequency oscillators) SYSCR0 <XTEN, RXTEN> XT1 Low-frequency fs XT2 oscillator SYSCR0 <XEN, RXEN> X1 High-frequency X2 oscillator SYS φT0 Figure 3.3.2 System Clock Block Diagram SYSCR0<WUEF> SYSCR2<WUPTM1:0> SIO0~SIO3 ...
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SFRs 7 SYSCR0 Bit symbol XEN (00E0H) Read/Write After reset 1 Function High- Low- frequency frequency oscillator oscillator 0: Stop 0: Stop 1: Active 1: Active Bit symbol SYSCR1 Read/Write (00E1H) After reset Function Bit symbol SYSCR2 Read/Write (00E2H) ...
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EMCCR0 Bit symbol PROTECT (00E3H) Read/Write R After reset 0 Function Protection Always write flag 0. 0: OFF 1: ON EMCCR1 Bit symbol (00E4H) Read/Write After reset Function Note: In case restarting the oscillator in the stop oscillation state ...
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System Clock Control Unit The system clock control unit generates system clock pulses (f the CPU core and internal I/O. It accepts either clock pulses generated by the high-frequency or low-frequency oscillator, respectively. SYSCR1<SYSCK> is used ...
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Example 1 Changing the system clock from high-frequency (fc) to low-frequency (fs) SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H (SYSCR2), X−11− −X−B LD SET 6, (SYSCR0) SET 2, (SYSCR0) WUP: BIT 2, (SYSCR0) JR NZ, WUP SET 3, ...
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Example 2 Changing the system clock from low-frequency (fs) to high-frequency (fc) SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H (SYSCR2), X−10− −X−B LD SET 7, (SYSCR0) SET 2, (SYSCR0) WUP: BIT 2, (SYSCR0) JR NZ, WUP RES 3, ...
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Prescaler Clock Control Unit The internal I/O functions (SIO0 to SIO3) are provided with a clock prescaler. The prescaler clock sources φT and φT0 are f 3.3.5 Noise Reduction Circuits The TMP91CW40 incorporates circuits providing the following features to ...
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Reducing drive capability of the low-frequency oscillator Purpose: To suppress noise generated by the low-frequency oscillator and to reduce power consumption of the low-frequency oscillator when an external resonator is connected. Block diagram: XT1 pin C1 Resonator C2 XT2 ...
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Preventing software or system lockups using a protection register Purpose: To prevent software or system lockups that may occur due to incoming noise. Applying protection causes specified SFRs to be write-protected, thus preventing the system recovery routine from becoming ...
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Standby Control (1) HALT mode Executing the HALT instruction causes the TMP91CW40 to enter one of the HALT modes–IDLE2, IDLE1 or STOP–as specified by the SYSCR2 <HALTM1:0> bits. The characteristics of IDLE2, IDLE1 and STOP modes are as follows: ...
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Wakeup signaling There are two ways to exit a HALT mode: An interrupt request or reset signal. Availability of wakeup signaling depends on the settings of the interrupt mask level bits, <IFF2:0>, of the CPU status register (SR) and ...
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Table 3.3.4 Wakeup Signaling Sources and Wakeup Operations Interrupt Masking HALT mode NMI INTWD Note 1) INT0,INT1, KWI0 to KWI3 INTALM0 to INTALM4 INTRTC INTTMR1 to INTTMR3, INTTMR5 to INTTMR8 INTRX0 to INTRX3, INTTX0 to INTTX3 INTAD RESET ♦: Execution ...
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Operation in HALT modes a. IDLE2 mode In IDLE2 mode, the CPU stops executing instructions and only the internal I/O functions enabled with the IDLE2 setting bits in respective SFRs are operational. Figure 3.3.5 shows example timings for exiting ...
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STOP mode In STOP mode, the whole TMP91CW40 stops, including the internal oscillator. Pin states in STOP mode depend on the setting of the SYSCR2<DRVE> bit, as shown in Table 3.3.6. Upon detection of wakeup signaling, the warm-up period ...
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Example: Entering STOP mode while using the low-frequency clock, exiting STOP mode with an NMI interrupt, and then resuming operation with the high-frequency clock Address SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H (SYSCR1), 08H FE8FFDH LD FE9000H LD ...
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Table 3.3.6 TMP91CW40 Input Buffer State Table I Port nput Function During Name Name Reset P50-52 KWI0-KWI2 OFF KWI3 P53 ADTRG P60 INT0 input P61 INT1 input − P62 P70 ECNT1 input P71 ECNT2 input P72 ECNT3 input P73 ECIN1 ...
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Interrupts Interrupt processing is controlled by the CPU interrupt mask register SR <IFF2:0> and the on-chip interrupt controller. The TMP91CW40 supports the following 43 interrupt sources: • 9 CPU internal interrupts (Software interrupts and interrupts triggered when an undefined ...
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Interrupt servicing Interrupt specified by micro DMA start vector? No Read interrupt vector V Clear interrupt request flag PUSH PC General PUSH SR interrupt SR<IFF2:0> ← Accepted servicing interrupt level + 1 INTNEST ← INTNEST + 1 PC ← (FFFF00H ...
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General Interrupt Servicing The CPU performs the following operations once it accepts an interrupt. These operations are the same as those performed by the TLCS-900/L and TLCS-900/H. (1) Reads an interrupt vector from the interrupt controller. If two or ...
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Default Priority Type 1 Reset or SWI0 instruction 2 SWI1 instruction 3 INTUNDEF: Undefined instruction or SWI2 instruction 4 SWI3 instruction 5 SWI4 instruction Non- 6 maskable SWI5 instruction 7 SWI6 instruction 8 SWI7 instruction 9 pin NMI 10 INTWD: ...
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Micro DMA In addition to general interrupt servicing, the TMP91CW40 supports a micro DMA feature. Interrupt requests specified with the micro DMA are assigned highest priority levels among maskable interrupts regardless of the priority levels actually set. The micro ...
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The micro DMA supports three transfer modes: 1 byte, 2 bytes or 4 bytes. For each transfer mode, the transfer source and destination addresses can be incremented, decremented or fixed after the transfer of a single unit of data. This ...
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Soft start In addition to interrupt sources, the micro DMA can also be started by software. This soft start feature enables the micro DMA to be started upon the detection of a write cycle to the DMAR register. Writing ...
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Transfer mode registers: DMAM0 to DMAM3 (DMAM0 to DMAM3 Mode ZZ Byte transfer Word transfer 4-byte transfer Reserved Destination address increment mode ....................... ...
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Interrupt Controller Figure 3.4.3 shows a block diagram of the interrupt circuit. The left-hand side of the diagram shows the interrupt controller while the right-hand side shows the CPU’s interrupt request signal circuit and halt wakeup circuit. For each ...
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Figure 3.4.3 Interrupt Controller Block Diagram 91CW40-36 TMP91CW40 2008-09-19 ...
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Interrupt priority registers Symbol Name Address INT0 & IADC INTAD 90H INTE0AD enable INT1& INTALM0 91H INTE1ALM0 enable INTALM1 & 92H INTEALM12 INTALM2 enable INTALM3 & 93H INTEALM34 INTALM4 enable INTTMR5 ITM6C & 94H INTETMR56 INTTMR6 enable INTTMR7 ITM8C ...
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Symbol Name Address 7 Interrupt ITX0C enable 9AH INTES0 R serial 0 0 Interrupt ITX1C enable 9BH INTES1 R serial 1 0 − INTRTC 9CH INTRTC − enable Interrupt ITX2C enable 9DH INTES2 R serial 2 0 Interrupt ITX3C enable ...
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External interrupt control Symbol Name Address 7 − 8CH (Read- 0 Interrupt IIMC input modify-write control instructions are prohibited) INT1 sensitivity 0 Edge-triggered 1 Level-sensitive INT0 sensitivity 0 Edge-triggered 1 Level-sensitive rising edge enable NMI 0 INT request occurs ...
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Micro DMA start vector registers A micro DMA start vector register specifies which interrupt source is assigned to micro DMA processing. The interrupt source having the micro DMA start vector specified in this register is assigned as a micro ...
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Precautions The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, after accepting an interrupt the CPU may fetch an instruction that clears the interrupt request flag for this interrupt before the interrupt is ...
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I/O Ports The TMP91CW40 has a total of 69 I/O port pins. All the port pins except a few share pins with alternate functions. They can be individually programmed as general-purpose I/O or dedicated I/O for the CPU or ...
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Port Pin Name Port 5 P50 to P53 Input port AN0 to AN3 inputs KWI0 to KWI3 inputs P53 input ADTRG Port 6 P60 Input port INT0 input P61 Input port Output port INT1 input P62 Input port Output port ...
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Table 3.5.3 I/O Port Settings (2/3) Port Pin Name Port 9 P90, P93 Input port Output port (CMOS output) Output port (Open-drain output) P91, P94 Input port Output port P92, P95 Input port Output port P90 TXD0 output (CMOS output) ...
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Table 3.5.4 I/O Port Settings (3/3) Port Pin Name Port 2 P00 to P07 Input port Output port SEG8 to SEG15 outputs Port 1 P10 to P17 Input port Output port SEG16 to SEG23 outputs Port 0 P20 to P27 ...
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Port 5 (P50 to P53) Port 4-bit input-only port that can also be used as analog input pins for the AD converter. P53 can also be used trigger input pin for the ...
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Port 6 (P60 to P62) The port 6 is composed of a 1-bit input port (P60) and 2-bit input/output ports (P61 and P62) of which inputs and outputs can be specified in units of bits. A reset allows the ...
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P61 (INT1) P61 can be used either as a general-purpose input/output port pin or an input pin for external interrupt INT1. Reset Direction control (Bitwise) P6CR write Function control (Bitwise) P6FC write S Output latch P6 write Selector P6 ...
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P62 ( ) ALARM P62 can be used either as a general-purpose input/output port pin or an output pin for the alarm function. Reset Direction control (Bitwise) P6CR write Function control (Bitwise) P6FC write Output latch ...
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Bit symbol P6 (0012H) Read/Write After reset 7 Bit symbol P6CR (0014H) Read/Write After reset Function 7 Bit symbol P6FC (0015H) Read/Write After reset Function Note: The P6CR and P6FC do not support read-modify-write operation. Port 6 Register 6 ...
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Port 7 (P70 to P75) Port 6-bit general-purpose I/O port. Each bit can be individually programmed for input or output. Reset operation initializes all pins to input port pins. In addition to functioning as a ...
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Bit symbol P7 (0013H) Read/Write After reset 7 Bit symbol P7CR (0016H) Read/Write After reset Function 7 Bit symbol P7FC (0017H) Read/Write After reset Function 7 Bit symbol P7FC2 (002DH) Read/Write After reset Function Note 1: The P7CR, P7FC ...
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Port 8 (P80 to P83) Port 4-bit general-purpose input/output port. Each bit can be individually programmed for input or output. Reset operation initializes all pins to input port pins. All bits in the output latch register ...
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Bit symbol P8 (0018H) Read/Write After reset 7 Bit symbol P8CR (001AH) Read/Write After reset Function 7 P8FC Bit symbol (001BH) Read/Write After reset Function Note: The P8CR and P8FC do not support read-modify-write operation. 7 ODE Bit symbol ...
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Port 9 (P90 to P95) Port 6-bit general-purpose input/output port. Each bit can be individually programmed for input or output. Reset operation initializes all pins as input port pins. All bits in the output latch register ...
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P91, P94 (RXD0, RXD1) P91 and P94 can be used either as input/output port pins or RXD input pins for serial channels 0 and 1. Reset Direction control (Bitwise) P9CR write S Output latch P9 write Selector P9 read ...
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Bit symbol P9 (0019H) Read/Write After reset 7 P9CR Bit symbol (001CH) Read/Write After reset Function 7 Bit symbol P9FC (001DH) Read/Write After reset Function Note 1: The P9CR and P9FC do not support read-modify-write operation. Note 2: To ...
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Port A (PA0 to PA5) Port 6-bit general-purpose input/output port. Each bit can be individually programmed for input or output. Reset operation initialize all pins as input port pins. All bits in the output latch register ...
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PA1, PA4 (RXD2, RXD3) PA1 and PA4 can be used either as general-purpose input/output port pins or RXD input pins for serial channels 2 and 3. Reset Direction control (Bitwise) PACR write S Output latch PA write Selector PA ...
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Bit symbol PA (001EH) Read/Write After reset 7 PACR Bit symbol (0020H) Read/Write After reset Function 7 Bit symbol PAFC (0021H) Read/Write After reset Function Note 1: The PACR and PAFC do not support read-modify-write operation. Note 2: To ...
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Port 2 (P20 to P27) Port 8-bit general-purpose input/output port. Each bit can be individually programmed for input or output. Reset operation initializes all pins as input port pins. All bits of the output latch register ...
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Bit symbol P27 P2 (0006H) Read/Write After reset 7 P2CR Bit symbol P27C (0008H) Read/Write After reset 0 Function 7 LCDSW1 Bit symbol SEG15C SEG14C (03D9H) Read/Write After reset 0 Function 0: Port 0: Port 1: SEG15 1: SEG14 ...
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Port 1 (P10 to P17) Port 8-bit general-purpose input/output port. Each bit can be individually programmed for input or output. Reset operation initializes all pins to input port pins. All bits of the output latch register ...
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Bit symbol P17 P1 (0001H) Read/Write After reset 7 P1CR Bit symbol P17C (0004H) Read/Write After reset 0 Function 7 LCDSW2 Bit symbol SEG23C (03DAH) Read/Write After reset 0 Function 0: Port 0: Port 1: SEG23 1: SEG22 Note: ...
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Port 0 (P00 to P07) Port 8-bit general-purpose input/output port. Each bit can be individually programmed for input or output. Reset operation initializes all pins as input port pins. All bits of the output latch register ...
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Bit symbol P07 P0 (0000H) Read/Write After reset 7 P0CR Bit symbol P07C (0002H) Read/Write After reset 0 Function 7 LCDSW3 Bit symbol SEG31C (03DBH) Read/Write After reset 0 Function 0: Port 0: Port 1: SEG31 1: SEG30 Note: ...
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Port B (PB0 to PB7) Port 8-bit general-purpose input/output port. Each bit can be individually programmed for input or output. Reset operation initializes all pins as input port pins. All bits of the output latch register ...
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Bit symbol PB7 PB (0024H) Read/Write After reset 7 PBCR Bit symbol PB7C (0025H) Read/Write After reset 0 Function 7 LCDSW4 Bit symbol SEG39C (03DCH) Read/Write After reset 0 Function 0: Port 1: SEG39 Note: The PBCR and LCDSW4 ...
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Timing Generator The timing generator generates various system clocks to be supplied to peripheral hardware based on the basic clock (fc or fs). (1) Configuration The timing generator consists of two counters, one for the high-frequency clock and one ...
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Divider Output ( ) DVO The timing generator is provided with a divider output feature which enables output of approximately 50% duty pulses. This feature is useful for driving a piezoelectric beeper. Divider output is implemented on the P72 ...
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Function latch P7FC2<P72F2> Function latch P7FC<P72F> Output latch P7<P72> Selector 13 5 fc fc fc fc/2 or fs/2 ...
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Timer/Counter The TMP91CW40 has three channels of 16-bit timers (TC1, TC2 and TC3). Each of the three channels operates independently, and is functionally equivalent. In the following sections, any references to TC1 also apply to other channels. 3.8.1 ...
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Control The timer/counter 1 (TC1) is controlled by the timer/counter 1 control registers (TC1CR1/TC1CR2), timer register (TREG1A) and internal window gate pulse setting register (TREG1B). Timer Register TREG1A (0941H, 0940H) TREG1AH (0941H) Internal Window Gate Pulse ...
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Timer/Counter 1 Control Register 2 TC1CR2 (0945H) SEG SGP Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care Note 2: Before setting the TC1CR2, be sure to stop the timer/counter (<TC1S> = 00). ...
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Source Clocks That Can Be Used in Each Operating Mode (NORMAL or IDLE2 mode) Operating mode Timer mode Event counter mode Pulse width measurement mode Frequency measurement mode (Slow or IDLE2 mode) Operating mode Timer mode Event counter mode Pulse ...
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Functional Description The timer/counter 1 has the following four operating modes: (1) Timer mode In the timer mode, the counter counts up on the rising edge of the internal clock. When a match between the counter value and the ...
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Programming sequences (Be sure to follow these sequences.) • Setting the timer mode with the system clock fc and the counter source clock fc/2 LD (TC1CR2),00H : Set the <TC1SEL> bit. (<TC1SEL> (TC1CR1),80H : Select the timer ...
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Event counter mode In the event counter mode, the counter counts up on the rising edge of the ECIN1 pin input. When a match between the counter value and the TREG1A register value is detected, an INTTMR1 interrupt is ...
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Pulse width measurement mode In the pulse width measurement mode, the counter counts up on the rising edge of the AND pulse of the ECIN1 pin input (window pulse) and the internal clock. The internal clock is selected by ...
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Programming sequences (Be sure to follow these sequences.) • Setting initial values LD (TC1CR2),00H : Set the <TC1SEL> bit. (<TC1SEL>=0) LD (TC1CR1),82H : Select the pulse width measurement mode. LD (TC1CR1),8AH : Set the source clock to fc/2 LD (TC1CR1),0CAH ...
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Frequency measurement mode The frequency measurement mode is used to measure the frequency of the ECIN1 pin input pulse. (In this mode, TC1CR1<TC1CK> should be set to external clock.) The counter counts up at the rising edge of the ...
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ECIN1 pin input Window gate pulse Counter 0 1 INTTMR1 interrupt Figure 3.8.8 Frequency Measurement Mode Timing Chart (Interrupt at the falling edge of the window gate pulse) ECIN1 pin input Window gate pulse Counter 0 1 INTTMR1 interrupt Figure ...
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ECIN1 pin input Window gate pulse FFFD FFFE Counter TC1SR<HEOVF> INTTMR1 interrupt Figure 3.8.11 Frequency Measurement Mode Timing Chart Programming sequences (Be sure to follow these sequences) • Setting initial values LD (TC1CR2),0A8H : <TC1SEL>=0 to select fc LD (TC1CR1),83H ...
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Timer/Counter The TMP91CW40 has four channels of 8-bit timers (TC5,TC6､TC7 and TC8). These channels are configured into two modules, each comprising two channels (TC5 and TC6; TC7 and TC8). Each module operates independently, and is functionally equivalent. In ...
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Control The timer/counter 5 is controlled by the timer/counter 5 control register 1 (TC5CR1), timer/counter 5 control register 2 (TC5CR2) and two 8-bit timer registers (TTREG5 and PWREG5). Timer Registers TTREG5 (0904H) R ...
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Timer/Counter 5 Control Register TC5CR2 − − − (0902H) TC5SEL Timer input clock control Note 1: Do not set <TC5SEL>=0 in SLOW or SLEEP mode. Note 2: Do not change TTREG5 when using for fs in ...
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The timer/counter 6 is controlled by the timer/counter 6 control register 1 (TC6CR1), timer/counter 6 control register 2 (TC6CR2), and two 8-bit timer registers (TTREG6 and PWREG6). Timer Register TTREG6 (0905H) R ...
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Timer/Counter 6 Control Register TC6CR2 − − − (0903H) TC6SEL Timer input clock control Note 1: Do not set <TC6SEL>=0 in SLOW or SLEEP mode. Note 2: Do not change TTREG6 when using for fs in ...
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Table 3.9.1 Source Clocks That Can Be Used in Each Operating Mode Operating Mode 8-bit timer 8-bit PWM 16-bit timer 16-bit PWM 16-bit PPG Note: In 16-bit mode (16-bit timer, 16-bit PWM, or 16-bit PPG), the source clock is specified ...
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Functional Description The timer/counters 5 and 6 (TC5 and TC6) have the following five operating modes: • 8-bit timer mode • 8-bit pulse width modulation (PWM) output mode • 16-bit timer mode • 16-bit pulse width modulation ...
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Programming sequences (Be sure to follow these sequences.) • Setting initial values LD (TC5CR2),00H : Set the <TC5SEL> bit. (<TC5SEL>=0 to select fc) LD (TC5CR1),30H : <TFF5>=0 (Drive TC5OUT pin high) <TC5CK>=011 (fc/2 <TC5M>=000 (8-bit timer mode) LD (TTREG5),55H : ...
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TC6) This mode is used to generate pulse width modulated (PWM) signals with a resolution of 8 bits. The counter counts up internal clock pulses. When a match between the ...
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Figure 3.9.5 8-Bit PWM Output Mode Timing Chart (TC5) 91CW40-93 TMP91CW40 2008-09-19 ...
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Programming sequences (Be sure to follow these sequences.) • Setting initial values LD (TC5CR2),00H : Set the <TC5SEL> bit. (<TC5SEL>=0 to select fc) LD (TC5CR1),62H : <TFF5>=0 (Drive TC5OUT pin high) <TC5CK>=110 (fc) <TC5M>=010 (8-bit PWM mode) LD (PWREG5),55H : ...
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TC6) In the 16-bit timer mode, the counter counts up internal clock pulses. The timer/counters 5 and 6 are cascaded to function as a 16-bit timer. After the timer is started by setting TC6CR1<TC6S>, ...
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Programming sequences (Be sure to follow these sequences.) • Setting initial values LD (TC6CR2),00H : Set the <TC6SEL> bit. (<TC6SEL>=0 to select fc) LD (TC5CR1),03H : <TC5M>=011 (16-bit mode) LD (TC6CR1),B4H : <TFF6>=1 (Drive TC6OUT pin low) <TC6CK>=011 (fc/2 <TC6M>=100 ...
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TC6) This mode is used to generate pulse width modulated (PWM) signals with a resolution of 16 bits. The timer/counters 5 and 6 are cascaded to realize the 16-bit ...
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Figure 3.9.7 16-Bit PWM Mode Timing Chart (TC5 + TC6) 91CW40-98 TMP91CW40 2008-09-19 ...
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Programming sequences (Be sure to follow these sequences.) • Setting initial values LD (TC6CR2),00H : Set the <TC6SEL> bit. (<TC6SEL>=0 to select fc) LD (TC5CR1),03H : <TC5M>=011 (16-bit mode) LD (TC6CR1),36H : <TFF6>=0 (Drive TC6OUT pin high) <TC6CK>=011 (fc/2 <TC6M>=110 ...
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TC6) In the 16-bit programmable pulse generation (PPG) mode, the timer/counters 5 and 6 are cascaded to function as a 16-bit timer. When a match between the counter value and the ...
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Figure 3.9.8 16-Bit PPG Mode Timing Chart (TC5 + TC6) 91CW40-101 TMP91CW40 2008-09-19 ...
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Programming sequences (Be sure to follow these sequences.) • Setting initial values LD (TC6CR2),00H : Set the <TC6SEL> bit. (<TC6SEL>=0 to select fc) LD (TC5CR1),03H : <TC5M>=011 (16-bit mode) LD (TC6CR1),37H :<TFF6>=0 (Drive TC6OUT pin high) LD (PWREG5),80H : Set ...
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Serial I/O (SIO) The TMP91CW40 contains four serial I/O channels (SIO0, SIO1, SIO2 and SIO3). For each channel, universal asynchronous receiver/transmitter (UART) mode or synchronous I/O interface mode can be selected. • I/O interface mode • UART mode In ...
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Mode 0 (I/O interface mode) Bit0 Transfer direction ● Mode 1 (7-bit UART mode) No parity Start Bit0 1 2 parity Start Bit0 1 2 ● Mode 2 (8-bit UART mode) No parity Start Bit0 1 ...
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Block Diagrams Prescaler φ φT2 φT8 Serial clock generator BR0CR <BR0CK1:0> BR0CR <BR0S3:0> φT0 φT2 φT8 φT32 f SYS SCLK0 input (Shared with P92) I/O interface mode SCLK0 output (Shared with P92) Receive counter ( ÷ ...
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Prescaler φ φT2 φT8 φT32 Serial clock generator BR1CR <BR1CK1:0> BR1CR <BR1S3:0> φT0 φT2 φT8 φT32 <BR1ADDE> Baud rate generator f SYS SCLK1 input (Shared with P95) I/O interface mode SCLK1 output (Shared with ...
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Prescaler φ φT2 φT8 Serial clock generator BR2CR <BR2CK1:0> BR2CR <BR2S3:0> φT0 φT2 φT8 φT32 Baud rate generator f SYS SCLK2 input (Shared with PA2) I/O interface mode SCLK2 output (Shared with PA2) Receive ...
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Prescaler φ φ T2 φ T8 φ T32 Serial clock generator BR1CR <BR1CK1:0> BR3CR <BR3S3:0> φ T0 φ T2 φ T8 φ T32 Baud Rate Generator f SYS SCLK3 input (Shared with PA5) ...
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SIO Components (1) Prescaler The SIO0 has a 6-bit prescaler that slows the rate of a clocking source to the serial clock generator. The prescaler clock source (φT0) has one-fourth the frequency of the clock selected by the <PRCK1:0> ...
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Baud rate generator The frequency used to transmit and receive data through the SIO0 is derived from the baud rate generator. The clock source for the baud rate generator can be selected from the 6-bit prescaler outputs (φT0, φT2, ...
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Integral clock division (divide-by- 12.288 MHz Input clock: φT2 Clock divisor N (BR0CR<BR0S3:0> BR0CR<BR0ADDE> Clocking conditions: System clock: The baud rate is determined as follows: Baud rate generator input clock Baud rate ...
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Table 3.10.3 UART Baud Rate Selection (when the baud rate generator is used and BR0CR<BR0ADDE> [MHz] Divisor N (Programmed in BR0CR<BR0S3:0> ) 9.830400 2 ↑ 4 ↑ 8 ↑ 0 12.288000 5 ↑ A 14.745600 2 ↑ ...
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Serial clock generator This block generates a basic clock (SIOCLK) for controlling transmit and receive operations. • I/O interface mode When the SCLK pin is configured as an output by clearing the SC0CR<IOC> bit to 0, the output clock ...
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Receive buffer The receive buffer is double-buffered to prevent overrun errors. Received data is serially shifted bit by bit into receive buffer 1. When a whole character (i.e bits, as programmed) is loaded into receive buffer ...
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Handshaking The SIO each have the clear-to-send ( enabled, the input must be low in order for a character to be transmitted. CTS This feature can be used for flow control to prevent overrun errors in the receiver. The SC0MOD0<CTSE> ...
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Transmit buffer Once the CPU loads a character into the transmit buffer (SC0BUF shifted out on the TXD output, with the least-significant bit first, clocked by the transmit shift clock TXDSFT from the transmit controller. When the ...
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Parity error <PERR> A parity error is reported when the parity bit attached to a character received on the RXD pin does not match the expected parity computed from the character transferred to receive buffer 2 (SC0BUF). 3. Framing ...
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SFRs 7 SC0MOD0 Bit symbol TB8 (0202H) Read/Write SC1MOD0 After reset 0 (020AH) SC2MOD0 Function Bit Handshake (0212H) transmitted control SC3MOD0 character 0: Disable (021AH) 1: Enable Figure 3.10.9 Serial Mode Control Register ...
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SC0CR Bit symbol RB8 (0201H) Read/Write R SC1CR After reset Undefined (0209H) SC2CR Function Bit Parity type (0211H) received 0: Odd SC3CR character 1: Even (0219H) A read -modify-write operation cannot be performed Note: All error ...
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Bit symbol BR0ADDE BR0CR (0203H) Read/Write BR1CR After reset 0 (020BH) + (16 − K) Function Always BR2CR write 0. /16 function (0213H) BR3CR 0: Disable (021BH) 1: Enable + (16 − K)/16 function 0 Disable 1 Enable ...
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SC0BUF TB7 (0200H) SC1BUF (0208H) SC2BUF 7 (0210H) SC3BUF RB7 (0218H) Note: The SCnBUF register does not support read-modify-write operation. Figure 3.10.12 Serial Transmit/Receive Buffer Register 7 Bit symbol I2S0 SC0MOD1 Read/Write R/W (0205H) SC1MOD1 After reset 0 (020DH) ...
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Operating Modes (1) Mode 0 (I/O interface mode) Mode 0 is used to increase the number of input/output pins. In this mode, the TMP91CW40 transmits or receives data to and from an external device, such as a shift register. ...
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Transmit operations In SCLK output mode, each time the CPU writes a character to the transmit buffer, the eight bits of the character are shifted out on the TXD0 pin and the synchronization clock is driven out from the ...
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Receive operations In SCLK output mode, each time the CPU picks up a character in receive buffer 2 clearing the receive-done interrupt flag (INTES0<IRX0C>), the synchronization clock is driven out from the SCLK pin to shift the next character ...
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Full-duplex transmit/receive operations To perform full-duplex transmit/receive operations, the receive interrupt priority level must be set to 0, with the transmit interrupt priority level set to an appropriate value (1 to 6). In the transmit interrupt service routine, receive ...
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Mode 1 (7-bit UART mode) Setting the SC0MOD0<SM1:0> field to 01 puts the SIO0 in 7-bit UART mode. In this mode, the parity bit can be added to the transmitted character, and the receiver can perform a parity check ...
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Mode 2 (8-bit UART mode) Setting the SC0MOD0<SM1:0> field to 10 puts the SIO0 in 8-bit UART mode. In this mode, the parity bit can be added to the transmitted character, and the receiver can perform a parity check ...
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Mode 3 (9-bit UART) Setting the SC0MOD0<SM1:0> field to 11 puts the SIO0 in 9-bit UART mode. In this mode, no parity bit can be added. The most-significant bit (9th bit) is stored in the SC0MOD0<TB8> bit in transmit ...
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Protocol 1. Put all the master and salve controllers in 9-bit UART mode. 2. Enable the receiver in each slave controller by setting the SC0MOD0 <WU> bit The master controller transmits an address character (i.e., select code) ...
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Example: Connecting a master controller and two slave controllers through a serial link using the system clock (f TXD RXD TXD Master Slave 1 Select code 00000001 • Master controller settings Main routine ← − − − − − − ...
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LCD Driver The TMP91CW40 contains a driver and a control circuit for directly driving a liquid crystal display (LCD). The LCD is connected using the following pins: a. Segment output pins b. Segment output/port (P0, P1, P2, PB) multiplexed ...
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Control The LCD driver is controlled by the LCD control register (LCDCR). The <EDSP> bit in the LCDCR is used to enable LCD display LCDCR (03D0H) EDSP BRES VFSEL SLF Base frequency [Hz] DUTY LCD drive ...
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LCDCR2 (03DEH) “0” “0” MSEG07 SEG0 to SEG7 pins MSEG07 output control Note 1: Do not set the <MSEG07> bit to 1 when the LCDCR<EDSP> bit is 1. Note 2: Except for bit 5, all the bits ...
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LCD drive method The LCD drive method can be selected from four types by the programming of the <DUTY> field in the LCDCR. The LCD drive method should be set in the initialization program according to the LCD to ...
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Frame frequency The frame frequency (f frequency, as shown in Table 3.11.1. The base frequency is selected by the LCDCR<SLF> field according to the basic clock frequencies fc and used. Table 3.11.1 Frame Frequency Settings a. ...
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LCD drive power supply To obtain the LCD drive power supply, the TMP91CW40 can use either the voltage reducer incorporated in the LCD driver that reduces the external reference voltage, or external divider resistors that divide the exernal reference ...
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Table 3.11.2 Current Carrying Capacities of the V2 Pin according to the Voltage Reducer Frequency (typ.) LCDCR Voltage Reducer <VFSEL> Frequency −1. μ fc/2 or fs/2 −1. μ fc/2 or ...
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LCD Display Operation (1) Display data setting The display data stored in the display data area is automatically read and sent to the LCD driver by hardware. The LCD driver generates segment and common signals according to the received ...
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Blanking When the <EDSP> bit in the LCDCR is cleared to 0, the COM pins are driven to GND level and the SEG pins are placed in a high-impedance state. When the TMP91CW40 enters STOP mode, the <EDSP> bit ...
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LCD Driver Control Method (1) Initial setting Figure 3.11.7 shows the flowchart for initializing the LCD driver. Figure 3.11.7 Initial Setting of LCD Driver Set P0, P1, ...
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Storing display data Display data is normally stored in the program memory (ROM) as fixed data, and transferred to the display data area by load instructions. Example 1: Table 3.11.4 shows the display data for displaying the numbers corresponding ...
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Example 2: Table 3.11.5 shows the display data for displaying the numbers shown in Table 3.11.4 using a 1/2 duty LCD, with the COM and SEG pins connected to the LCD as shown in Figure 3.11.9. SEG3 Figure 3.11.9 Example ...
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TMP91CW40 2008-09-19 ...
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TMP91CW40 2008-09-19 ...
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Real time clock (RTC) 3.12.1 Function description for RTC 1) Clock function (hour, minute, second) 2) Calendar function (month and day, day of the week, and leap year 12-hour (AM/PM) clock function 4) +/－ 30 second ...
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Control registers Table 3.12.1 PAGE 0 (Clock function) registers Symbol Address Bit7 Bit6 SECR 0320H 40 sec MINR 0321H 40 min HOURR 0322H 20 hours/ DAYR 0323H DATER 0324H Day 20 MONTHR 0325H YEARR 0326H Year 80 Year 40 ...
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Detailed explanation of control register RTC is not initialized by system reset. Therefore, all registers must be initialized at the beginning of the program. (1) Second column register (for PAGE0 only) 7 SECR Bit symbol (0320H) Read/Write Reset State ...
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Minute column register (for PAGE0/1) 7 MINR Bit symbol (0321H) Read/Write Reset State Function "0" is read MI6 MI5 MI4 Undefined 40 min, 20 min, 10 min, column column column ...
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Hour column register (for PAGE0/ case of 24-hour clock mode (MONTHR<MO0>= “1”) 7 HOURR Bit symbol (0322H) Read/Write Reset State "0" is read. Function 2. In case of 12-hour clock mode (MONTHR<MO0>= “0”) 7 HOURR Bit symbol ...
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Day of the week column register (for PAGE0/1) 7 DAYR Bit symbol (0323H) Read/Write Reset State Function (5) Day column register (PAGE0/1) 7 DATER Bit symbol (0324H) Read/Write Reset State "0" is read. Function "0" is ...
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Month column register (for PAGE0 only) 7 MONTHR Bit symbol (0325H) Read/Write Reset State "0" is read. Function (7) Select 24-hour clock or 12-hour clock (for PAGE1 only) 7 MONTHR Bit symbol (0325H) Read/Write Reset State Function 6 5 ...
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Year column register (for PAGE0 only) 7 YEARR YE7 Bit symbol (0326H) Read/Write Reset State Function 80 Years (9) Leap-year register (for PAGE1 only) 7 YEARR Bit symbol (0326H) Read/Write Reset State Function YE6 YE5 YE4 ...
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PAGE register (for PAGE0/1) 7 PAGER INTENA Bit symbol (0327H) R/W Read/Write 0 Reset State A Read- Interrupt Function modify- write 0: Disable operation 1: Enable cannot be performed Note: Please keep the setting order below of <ENATMR>, <ENAAML> ...
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Operational description (1) Reading clock data 1. Using 1Hz interrupt 1Hz interrupt and the count up of internal data synchronize. Therefore, data can read correctly if reading data after 1Hz interrupt occurred. 2. Using two times reading There is ...
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Writing clock data When a carry over occurs during a write operation, the data cannot be written correctly. Please use the following method to ensure data is written correctly. 1. Using 1Hz interrupt 1Hz interrupt and the count up ...
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Disabling the clock A clock carry over is prohibited when “0” is written to PAGER<ENATMR> in order to prevent malfunction caused by the Carry hold circuit. While the clock is prohibited, the Carry hold circuit holds a one sec. ...
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Explanation of the interrupt signal and alarm signal The alarm function used by setting the PAGE1 register and outputting either of the following three signals from outputs a 1-shot pulse when the falling edge is detected. RTC is not ...
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With 1Hz output clock RTC outputs a clock of 1Hz to RESTR<DIS1HZ>= “0”, <DIS16HZ>= “1”. RTC also generates an INTRTC interrupt on the falling edge of the clock. (3) With 16Hz output clock RTC outputs a clock of 16Hz ...
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Melody/Alarm Generator (MLD) The TMP91CW40 contains a melody/alarm generator (MLD) for generating melody and alarm waveforms. The MLD can output either alarm or melody waveforms on the The alarm generator uses a 15-bit free-running counter that can generate five ...
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Block Diagram [Melody generator] MELFH <MELON> Low-frequency clock 32.768 kHz MELALMC <FC1:0> [Alarm generator] Internal data bus MELFH, MELFL registers Invert Comparator (CP0) Stop & clear Clear 12-bit counter (UC0) Edge detector 15-bit free-running counter (UC1) 4096 Hz 8-bit ...
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SFRs 7 ALM Bit symbol AL8 (0330H) Read/Write After reset 0 Function 7 Bit symbol FC1 MELALMC (0331H) Read/Write R/W After reset 0 Function Free-running counter control 00: Hold 01: Resume 10: Clear & stop 11: Clear & start ...
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Operational Description 3.13.3.1 Melody Generator Based on the low-frequency clock (32.768 kHz), the melody generator can generate clock waveforms at frequencies from 5461 Hz on the connecting an external speaker, the melody output function can easily ...
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Alarm Generator The alarm generator can generate eight patterns of alarm waveforms at a frequency of 4096 Hz modulated from the low-frequency clock (32.768 kHz). These waveforms are output on the MLDALM connecting an external speaker, the alarm output ...
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Pattern Output Waveforms: No Inversion) AL1 pattern (Continuous output) 1 AL2 pattern (31.25 ms/8 times/1 s) 31. AL3 pattern (500 ms/once) 1 AL4 pattern (62.5 ms/twice AL5 pattern (62.5 ms/3 times/1 s) 62.5 ...
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Program Patch Logic The TMP91CW40 has a program patch logic, which enables the user to fix the program code in the internal ROM. Patch program code must be read into the internal RAM from external memory during the startup ...
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SFRs The program patch logic consists of six banks (0 to 5). Each bank is provided with three bytes of address compare registers (ROMCMPx0 to ROMCMPx2) and two bytes of patch code registers (ROMSUBxL and ROMSUBxH). 7 ROMCMP00 Bit ...
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ROMCMP10 Bit symbol ROMC07 (0408H) Read/Write After reset 0 Function 7 ROMCMP11 Bit symbol ROMC15 (0409H) Read/Write After reset 0 Function 7 ROMCMP12 Bit symbol ROMC23 (040AH) Read/Write After reset 0 Function 7 ROMSUB1L Bit symbol ROMS07 (040CH) Read/Write ...
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ROMCMP20 Bit symbol ROMC07 (0410H) Read/Write After reset 0 Function 7 ROMCMP21 Bit symbol ROMC15 (0411H) Read/Write After reset 0 Function 7 ROMCMP22 Bit symbol ROMC23 (0412H) Read/Write After reset 0 Function 7 ROMSUB2L Bit symbol ROMS07 (0414H) Read/Write ...
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ROMCMP30 Bit symbol ROMC07 (0418H) Read/Write After reset 0 Function 7 ROMCMP31 Bit symbol ROMC15 (0419H) Read/Write After reset 0 Function 7 ROMCMP32 Bit symbol ROMC23 (041AH) Read/Write After reset 0 Function 7 ROMSUB3L Bit symbol ROMS07 (041CH) Read/Write ...
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ROMCMP40 Bit symbol ROMC07 (0420H) Read/Write After reset 0 Function 7 ROMCMP41 Bit symbol ROMC15 (0421H) Read/Write After reset 0 Function 7 ROMCMP42 Bit symbol ROMC23 (0422H) Read/Write After reset 0 Function 7 ROMSUB4L Bit symbol ROMS07 (0424H) Read/Write ...
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ROMCMP50 Bit symbol ROMC07 (0428H) Read/Write After reset 0 Function 7 ROMCMP51 Bit symbol ROMC15 (0429H) Read/Write After reset 0 Function 7 ROMCMP52 Bit symbol ROMC23 (042AH) Read/Write After reset 0 Function 7 ROMSUB5L Bit symbol ROMS07 (042CH) Read/Write ...
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Operational Description (1) Replacing data Two consecutive bytes of data can be replaced for each bank. A two-byte sequence to be replaced must start at an even address. If only a single byte at an even or odd address ...
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Replacing 33H at address FF1233H with BBH ← ROMCMP00 ← ROMCMP01 ← ROMCMP02 ← ROMSUB0L ...
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Replacing 77H at address FF1237H with EEH and 88H at address FF1238H with FFH (requiring two banks ← ROMCMP00 ← ROMCMP01 ← ROMCMP02 1 ...
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Using an interrupt to cause a branch A wider range of program code can also be fixed using a software interrupt (SWI). With patch code loaded into the internal RAM, the program patch logic can be used to replace ...
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Internal I/O 001000H Internal RAM 001500H Patch code 0015EFH 002000H Internal area (Access not allowed) FE0000H Internal ROM FF5000H 55H FF5001H AAH ・ Bug area ・ ・ ・ FF507FH FF5080H FFFF00H Vector table FFFF04H 001500H FFFF07H Figure 3.14.12 Example ...
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Key-On Wakeup In addition to the INT0 and INT1 interrupt source pins, the TMP91CW40 has four interrupt channels that enable the pressing of a key to terminate HALT mode, called key-on wakeup interrupts (KWI). Figure 3.15.1 shows a block ...
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SFRs 7 KWIEN Bit symbol (03A0H) Read/Write After reset Function 7 KWICR Bit symbol (03A1H) Read/Write After reset Function Note: The KWIEN and KWICR registers do not support read-modify-write operation. 3.15.3 Control The P50 to P53 pins function as ...
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Analog-to-Digital Converter (AD Converter) The TMP91CW40 has a 10-bit successive-approximation analog-to-digital converter (AD converter) having 4 channels of analog inputs. Figure 3.16.1 shows a block diagram of the AD converter. The four analog input channels (AN0 to AN3) can ...
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Control Registers The AD converter is controlled by the AD mode control registers (ADMOD0 and ADMOD1). AD conversion results are stored in four conversion result high/low register pairs (ADREG04H/L, ADREG15H/L, ADREG26H/L and ADREG37H/L). Figure 3.16.2 to Figure 3.16.5 show ...
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Bit symbol VREFON ADMOD1 (02B1H) Read/Write R/W After reset 0 Function VREF ADC control operation in IDLE2 mode 0: OFF 0: Stop Operation Note: The AN3 pin is shared with the enabled (i.e., ADMOD1<ADTRGE> ...
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Bit symbol ADR01 ADREG04L (02A0H) Read/Write R After reset Undefined Function Lower 2 bits conversion result 7 ADREG04H Bit symbol ADR09 (02A1H) Read/Write After reset Function 7 ADREG15L Bit symbol ADR11 (02A2H) Read/Write R After reset ...
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Bit symbol ADR21 ADREG26L (02A4H) Read/Write R After reset Undefined Function Lower 2 bits conversion result 7 Bit symbol ADR29 ADREG26H (02A5H) Read/Write After reset Function 7 Bit symbol ADR31 ADREG37L (02A6H) Read/Write R After reset ...
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Operational Description (1) Analog reference voltages The VREFH and VREFL pins provide the reference voltages for the AD converter. These pins establish the full-scale range for the internal resistor string, which divides the range into 1024 steps. The digital ...
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Starting an AD conversion The AD converter starts a conversion when ADMOD0<ADS> is set when a falling edge is applied to the conversion starts, the AD conversion busy flag (ADMOD0<ADBF>) is set to 1. Setting the ...
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Fixed-channel continuous conversion mode This mode is selected by programming the <REPEAT> and <SCAN> bits in the ADMOD0 to 10. In fixed-channel continuous conversion mode, the AD converter repeatedly converts a single selected channel. When the conversion process is ...
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Conversion time The conversion process requires 84 conversion states per channel (6.2 μs when MHz). (6) Storing and reading AD conversion results AD conversion results are stored in the conversion result high/low register pairs (ADREG04H/L to ...
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Programming examples: a. Converting the analog input voltage on the AN3 pin to a digital value and storing the converted value in a memory location (1800H) using the AD interrupt (INTAD) service routine Settings in the main routine 7 6 ...
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Watchdog Timer (WDT) The TMP91CW40 contains a watchdog timer. The watchdog timer is used to regain control of the system in the event of software or system lockups due to spurious noise, etc. When a watchdog timer time-out occurs, ...
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Operational Description The watchdog timer is a kind of timer that generates an interrupt request if it times out. The watchdog timer allows the user to program the time-out period in the <WDTP1:0> field in the WDMOD register. While ...
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Control Registers The watchdog timer is controlled by two registers called WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) a. Time-out period <WDTP1:0> This 2-bit field determines the duration of the watchdog timer time-out interval. A reset initializes ...
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Bit symbol WDTE WDMOD Read/Write R/W (0300H) After reset 1 Function WDT control 0: Disable 1: Enable Figure 3.17.4 Watchdog Timer Mode Register 7 Bit symbol WDCR Read/Write (0301H) After reset Read-modify- Function write instructions cannot be used. Figure ...
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Electrical Characteristics 4.1 Absolute Maximum Ratings Parameter Supply voltage Input voltage Output current (per pin) Output current (per pin) Output current (total) Output current (total) Power dissipation (Ta = 85°C) Soldering temperature (10 s) Storage temperature Operating temperature Note: ...
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DC Electrical Characteristics (1/2) Parameter Symbol Power supply voltage AVCC = DVCC VCC AVSS = DVSS = 0 V P0, P1, P2, P5, P62, P7, P8, VIL1 P9, PA RESET NMI VIL2 P60(INT0), P61(INT1) AM0, AM1 ...
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DC Electrical Characteristics (2/2) Parameter Symbol Input leakage current ILI Output leakage current ILO Power down voltage VSTOP (while RAM is being backed up in STOP mode) RRST RESET pull-up resistor Pin capacitance CIO Schmitt width VTH , , INT0, ...
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AD Conversion Electrical Characteristics Parameter Analog reference voltage（＋） Analog reference voltage（－） Analog input voltage Analog current for analog reference voltage <VREFON> (VREFL=0V) <VREFON> Total error (not including quantization error) Note 1: 1 LSB = (VREFH ...
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SIO Timing (I/O Interface Mode) (1) SCLK input mode Parameter Symbol SCLK period SCLK rising → Output Data /falling edge* SCLK rising → Output Data hold /falling edge* SCLK rising → Input Data hold /falling edge* SCLK rising → ...
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Timer/Counter Input (ECIN) Characteristics Parameter Symbol Frequency measurement mode VDD =2.7 to 3.6 V Timer/counter input t TC1 (ECIN1 to ECIN3 input) Frequency measurement mode VDD =2.2 to 2.7 V 4.6 Interrupts (1) , INT0 and INT1 interrupts NMI ...