TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 177

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

(2) Using an interrupt to cause a branch
Correction procedure:
Example: Fixing a program within a range from FF5000H to FF507F
With patch code loaded into the internal RAM, the program patch logic can be used to
replace program code at a specified address with a single-byte SWI instruction, which
causes a branch to the patch program.
developed with internal RAM addresses specified as SWI vector addresses.
address of the program code that is to be fixed. If it is an even address, store an SWI
instruction code (e.g., SWI: F9H) in the ROMSUB0L. If the start address is an odd
address, store an SWI instruction code in the ROMSUB0H and the current ROM data
at the preceding even address in the ROMSUB0L.
rewrites the saved PC value so that it points to the address following the patch code,
and then executes a RETI.
0015EFH). Store the start address (FF5000H) of the ROM area to be fixed in the
ROMCMP00 to ROMCMP02. Store the SWI1 instruction code (F9H) in the
ROMSUB0L and the current data at FF5001H (AAH) in the ROMSUB0H. When the
CPU address matches the value stored in the ROMCMP00 to ROMCMP02, the
program patch logic replaces the ROM-based code at FF5000H with F9H. The CPU
then executes the SWI1 instruction, which causes a branch to 001500H in the internal
RAM area. After executing the patch program the CPU finally rewrites the saved PC
value to FF5080H and executes a RETI.
registers, the program patch logic disables RD output to the masked ROM and drives
out the SWI instruction code to the internal bus. Upon fetching the SWI code, the
CPU makes a branch to the internal RAM area to execute the preloaded code.
to address 001500H (in the internal RAM area).
A wider range of program code can also be fixed using a software interrupt (SWI).
Note that this method can only be used if the original masked ROM has been
Load the address compare registers (ROMCMP00 to ROMCMP02) with the start
When the CPU address matches the value stored in the ROMCMP00 to ROMCMP02
At the end of the patch program executed from the internal RAM, the CPU directly
The following shows an example:
Before developing the original masked ROM, set the SWI1 vector reference address
Use the startup routine to load the patch code to the internal RAM (001500H to
91CW40-175
TMP91CW40
2008-09-19