TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 59

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

P9
(0019H)
P9CR
(001CH)
P9FC
(001DH)
ODE
(002FH)
Note 1: The P9CR and P9FC do not support
Note 2: To specify the TXD pin as an open-drain
read-modify-write operation.
output, write 1 to bit 4 (for the TXD0 pin) or
bit 5 (for the TXD1 pin) of the ODE
register. The P91/RXD0 and P94/RXD1
pins do not have a register bit for selecting
the port or SIO function. The input to these
pins is always directed to the SIO as serial
receive data even when they are used as
general-purpose input pins.
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
PA3
open-drain
output
0: Disable
1: Enable
ODEA3
7
7
7
7
0
PA0
open-drain
output
0: Disable
1: Enable
ODEA0
6
6
6
6
0
Figure 3.5.14 Port 9 Registers
0: Port
1: SCLK1
P93
open-drain
output
0: Disable
1: Enable
ODE93
output
P95C
P95F
P95
Port 9 Function Register
W
Port 9 Control Register
5
5
5
5
0
0
0
Open-Drain Register
91CW40-57
Data from external port (Output latch register is set to 1.)
Port 9 Register
P90
open-drain
output
0: Disable
1: Enable
ODE90
P94C
P94
4
4
4
4
0
0
R/W
0: Input
0: Port
1: TXD1
P83
open-drain
output
0: Disable
1: Enable
ODE83
P93C
P93F
P93
W
3
3
3
3
0
0
0
R/W
W
0: Port
1: SCLK0
P82
open-drain
output
0: Disable
1: Enable
ODE82
output
P92C
1: Output
P92F
P92
W
2
2
2
2
0
0
0
Open-drain output setting
P81
open-drain
output
0: Disable
1: Enable
P90 TXD0 output setting
P92 SCLK0 output setting
P93 TXD1 output setting
P95 SCLK1 output setting
0 Disable
1 Enable
P9FC<P90F>
P9CR<P90C>
P9FC<P92F>
P9CR<P92C>
P9FC<P93F>
P9CR<P93C>
P9FC<P95F>
P9CR<P95C>
ODE81
P91C
Port 9 input/output setting
P91
0 Input
1 Output
1
1
1
1
0
0
0: Port
1: TXD0
P80
open-drain
output
0: Disable
1: Enable
ODE80
TMP91CW40
P90C
P90F
P90
W
0
0
0
0
0
0
0
2008-09-19
1
1
1
1
1
1
1
1