TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 35

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

Symbol
DMAR
Software
request
register
Name
DMA
(2) Soft start
(3) Transfer control registers
Channel 0
Channel 3
DMAS0
DMAD0
DMAS3
DMAD3
micro DMA transfer isn’t started yet.
that has been once started continues transferring data until the micro DMA transfer
counter reaches zero. If execute soft start during micro DMA transfer by interrupt
source, micro DMA transfer counter doesn’t change. Don’t use Read-modify-write
instruction to avoid writing to other bits by mistake.
destination addresses. Use the “LDC cr, r” instruction to set data in these registers.
soft start feature enables the micro DMA to be started upon the detection of a write
cycle to the DMAR register.
corresponding channel. When the transfer is completed, the bit is automatically
cleared to 0. Only one channel can be started at a time. (Do not write 1 to more than
one bit in the DMAR register at the same time.)
32 bits
In addition to interrupt sources, the micro DMA can also be started by software. This
Writing 1 to each bit in the DMAR register starts a micro DMA transfer in the
A DMAR register bit must be verified to be 0 before it can be set to 1 again. If read 1,
When a burst transfer is specified in the DMAB register, the micro DMA channel
The following registers in the CPU are used to control the transfer source and
are prohibited)
modify-write
Address
instructions
(Read-
89H
DMAC0
DMAC3
16 bits
DMAM0
DMAM3
8 bits
7
Transfer source address register 0; Only lower 24 bits are used.
Transfer destination address register 0; Only lower 24 bits are used.
Transfer counter register 0; 1 to 65536
Transfer mode register 0
Transfer source address register 3
Transfer destination address register 3
Transfer counter register 3
Transfer mode register 3
6
91CW40-33
5
4
DMAR3
3
0
DMAR2
1: DMA request
2
0
R/W
DMAR1
1
TMP91CW40
0
2008-09-19
DMAR0
0
0