TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 117

no-image

TMP91xy40FG

Manufacturer Part Number
TMP91xy40FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy40FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/F
Rom Combinations
128
Ram Combinations
4
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
4
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
3
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
61
Power Supply Voltage(v)
2.2 to 3.6
Note: a. When
Write to the transmit
buffer
b. The transmitter starts transmission at the first falling edge of the TXDCLK clock after the
SIOCLK
TXDCLK
TXD
character has been sent.
CTS
Handshaking
enabled, the
This feature can be used for flow control to prevent overrun errors in the receiver.
The SC0MOD0<CTSE> bit enables and disables the
controller stops transmission upon completion of the current character until
goes low again. The transmit controller generates the INTTX0 interrupt to notify
the CPU that the transmit buffer is empty. After the CPU loads the next character
into the transmit buffer, the transmit controller remains in idle state until it
detects
serve as the
character,
stop the transmitting device from sending the next character. This way, the user
can easily implement a two-way handshake protocol.
CTS
The SIO each have the clear-to-send (
If the
Although there do not have the
CTS
input of the transmitting device. Once the receiving device has received a
Figure 3.10.8
a
No transmission takes
goes high in the middle of transmission, the transmiter stops transmission after the current
CTS0
place during this
period.
CTS0
Transmitting device
RTS
Figure 3.10.7 Handshaking Signals
CTS
TMP91CW40
going low.
RTS
pin goes high in the middle of a transmission, the transmit
13
should be set to high in the receive-done interrupt to temporarily
input must be low in order for a character to be transmitted.
pin. The receiving device uses the
CTS
14
TXD
CTS
b
91CW40-115
(Clear-to-send) Signal Timing
15
16
1
RTS
Start bit
2
pin, any general-purpose port pins can
CTS
3
) pin. When the
RXD
RTS
Receiving device
CTS
TMP91CW40
14
RTS
(Any port)
operation.
15
output to control the
16
CTS
CTS
TMP91CW40
1
operation is
signal goes low.
2008-09-19
Bit0
2
CTS0
3

Related parts for TMP91xy40FG