TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 9

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

3.
3.1
3.1.1
Operation
This section describes the functions and basic operation of the TMP91CW40.
description of the CPU, refer to “TLCS-900/L1 CPU” in the preceding chapter.
below.
CPU
The TMP91CW40 contains a high-performance 16-bit CPU (900/L1 CPU). For a detailed
Functions unique to the TMP91CW40 not covered in “TLCS-900/L1 CPU” are described
Reset Operation
voltage range, and that the internal high-frequency oscillator has stabilized. Then, set the
power to the TMP91CW40, hold the
with the power supply voltage within the operating voltage range and the internal
high-frequency oscillator oscillating stably.
operations as a result of a reset:
PC. CPU internal registers other than the above are not changed.
RESET
Note: Reset operation does not affect the contents of the internal RAM or the CPU registers other than PC, SR and
The internal I/O peripherals, ports and other pins are initialized as follows upon a reset:
To reset the TMP91CW40, ensure that the power supply voltage is within the operating
Reset operation initializes the system clock f
After the reset state is released, the CPU starts executing instructions according to the
Figure 3.1.1 shows reset timings of the TMP91CW40.
•
•
•
•
•
•
•
XSP.
input to low level for at least 10 system clocks (1µs at 27 MHz). After turning on the
Sets the program counter (PC) according to the reset vector stored at addresses
FFFF00H to FFFF02H.
Sets the stack pointer (XSP) to 100H.
Sets the <IFF2:0> bits of the status register (SR) to 111 (setting the interrupt level
mask register to level 7).
Sets the <MAX> bit of the status register (SR) to 1 (selecting maximum mode).
Clears the <RFP2:0> bits of the status register (SR) to 000 (selecting register bank
0).
All internal I/O registers are initialized.
All port pins, including those multiplexed with internal I/O functions, are
configured either as general-purpose inputs or general-purpose outputs.
PC<7:0>
PC<15:8>
PC<23:16>
←
←
←
Value at address FFFF00H
Value at address FFFF01H
Value at address FFFF02H
91CW40-7
RESET
input at low level for at least 10 system clocks
SYS
to fc/2. The CPU performs the following
TMP91CW40
2008-09-19