TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 99

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

3.9
TC6CR2
<TC6SEL>= 0
fc/2
fc/2
fc/2
fc/2
fc/3
fc/2
fc
(4) 16-bit pulse width modulation (PWM) output mode (TC5 + TC6)
11
7
5
3
resolution of 16 bits. The timer/counters 5 and 6 are cascaded to realize the 16-bit
PWM output mode.
PWREG6) value is detected, the timer flip-flop 6 (F/F6) is toggled. The counter then
continues counting up. When an overflow occurs, the timer F/F6 is toggled again, the
counter is cleared, and an INTTMR6 interrupt is generated.
shift register, enabling the PWREG5 and PWREG6 values to be changed while the
timer is running. While the timer is running, the values written to the PWREG5 and
PWREG6 are shifted into the shift register and become valid by an INTTMR6
interrupt. This feature makes it possible to change the pulse width continuously. When
the timer is not running, the values written to the PWREG5 and PWREG6 are
immediately shifted into the shift register. When writing to the PWREG5 and
PWREG6, be sure to write in the order of lower byte (PWREG5) and upper byte
(PWREG6). (It is also possible to change only the lower or upper byte of the timer
register.)
output, the shift register value is returned instead of the value set in the PWREG5 and
PWREG6. This means that the new value written to the PWREG5 and PWREG6
cannot be read out until an INTTMR6 interrut occurs; up to that point the previous
PWREG5 abd PWREG6 values are read out.
Note 1: In the PWM mode, the timer registers PWREG6 and PWREG5 should be written to immediately after an
Note 2: If the timer is stopped during PWM output, the TC6OUT pin retaines its current output state. After the
Source Clock
This mode is used to generate pulse width modulated (PWM) signals with a
When a match between the counter value and the timer register (PWREG5,
In the PWM mode, the PWREG5 and PWREG6 registers are serially connected to a
When a read instruction is executed on the PWREG5 and PWREG6 during PWM
INTTMR6 interrupt occurred (normally in the INTTMR6 interrupt service routine). If a write to the
PWREG6 and PWREG5 and an INTTMR6 interrupt occur simultaneously, an unstable value is shifted
into the shift register, causing unexpected pulses to be generated until the next INTTMR6 interrupt
occurs.
timer stops, the TC6OUT pin state can be chagned to a desired level by using TC6CR1<TFF6>. Be
careful not to set TC6CR1<TFF6> at the same time as stopping the timer.
(For example, the TC6OUT pin should be fixed to high level while the timer/counter is not running.)
fs/2
fs
TC6CR2
<TC6SEL>= 1
3
RES
RES
Table 3.9.7 16-Bit PWM Output Mode
3, (TC6CR1)
7, (TC6CR1)
fc = 27 MHz
296.3 ns
111.1 ns
75.9 μs
74.1 ns
37.0 ns
4.7 μs
1.2 μs
91CW40-97
図 3.9.1図 3.9.2図 3.9.3図 3.9.4図 3.9.5図 3.9.6表 3.9.1表 3.9.2表 3.9.3表 3.9.4表 3.9.5表 3.9.6
Resolution
: Stop the timer & clear the counter.
: <TFF6>=0 (Drive TC6OUT pin high)
fs = 32.768 kHz
244.14μs
30.52 μs
−
−
−
−
−
fc = 27 MHz
310.7 ms
4.97 s
77.7 ms
19.4 ms
7.3 ms
4.9 ms
2.4 ms
Repeat Cycle
fs = 32.768 kHz
16 s
2 s
−
−
−
−
−
TMP91CW40
2008-09-19